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bd2122ca35
Add PRCM partition, CM instance register address offset, and clockdomain register address offset to each OMAP4 struct clockdomain record. Add OMAP4 clockdomain code to use this new data to access registers properly. While here, clean up some nearby clockdomain code to allocate auto variables in my recollection of Linus's preferred style. The autogeneration scripts have been updated. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Rajendra Nayak <rnayak@ti.com> Cc: Santosh Shilimkar <santosh.shilimkar@ti.com> Cc: Benoît Cousson <b-cousson@ti.com> Tested-by: Rajendra Nayak <rnayak@ti.com> Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
215 lines
6.6 KiB
C
215 lines
6.6 KiB
C
/*
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* OMAP4 CM instance functions
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*
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* Copyright (C) 2009 Nokia Corporation
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* Paul Walmsley
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This is needed since CM instances can be in the PRM, PRCM_MPU, CM1,
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* or CM2 hardware modules. For example, the EMU_CM CM instance is in
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* the PRM hardware module. What a mess...
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <plat/common.h>
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#include "cm.h"
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#include "cm1_44xx.h"
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#include "cm2_44xx.h"
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#include "cm44xx.h"
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#include "cminst44xx.h"
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#include "cm-regbits-34xx.h"
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#include "cm-regbits-44xx.h"
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#include "prcm44xx.h"
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#include "prm44xx.h"
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#include "prcm_mpu44xx.h"
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static u32 _cm_bases[OMAP4_MAX_PRCM_PARTITIONS] = {
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[OMAP4430_INVALID_PRCM_PARTITION] = 0,
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[OMAP4430_PRM_PARTITION] = OMAP4430_PRM_BASE,
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[OMAP4430_CM1_PARTITION] = OMAP4430_CM1_BASE,
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[OMAP4430_CM2_PARTITION] = OMAP4430_CM2_BASE,
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[OMAP4430_SCRM_PARTITION] = 0,
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[OMAP4430_PRCM_MPU_PARTITION] = OMAP4430_PRCM_MPU_BASE,
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};
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/* Read a register in a CM instance */
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u32 omap4_cminst_read_inst_reg(u8 part, s16 inst, u16 idx)
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{
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BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
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part == OMAP4430_INVALID_PRCM_PARTITION ||
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!_cm_bases[part]);
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return __raw_readl(OMAP2_L4_IO_ADDRESS(_cm_bases[part] + inst + idx));
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}
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/* Write into a register in a CM instance */
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void omap4_cminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx)
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{
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BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
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part == OMAP4430_INVALID_PRCM_PARTITION ||
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!_cm_bases[part]);
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__raw_writel(val, OMAP2_L4_IO_ADDRESS(_cm_bases[part] + inst + idx));
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}
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/* Read-modify-write a register in CM1. Caller must lock */
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u32 omap4_cminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, s16 inst,
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s16 idx)
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{
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u32 v;
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v = omap4_cminst_read_inst_reg(part, inst, idx);
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v &= ~mask;
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v |= bits;
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omap4_cminst_write_inst_reg(v, part, inst, idx);
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return v;
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}
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/*
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*
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*/
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/**
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* _clktrctrl_write - write @c to a CM_CLKSTCTRL.CLKTRCTRL register bitfield
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* @c: CLKTRCTRL register bitfield (LSB = bit 0, i.e., unshifted)
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* @part: PRCM partition ID that the CM_CLKSTCTRL register exists in
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* @inst: CM instance register offset (*_INST macro)
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* @cdoffs: Clockdomain register offset (*_CDOFFS macro)
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*
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* @c must be the unshifted value for CLKTRCTRL - i.e., this function
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* will handle the shift itself.
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*/
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static void _clktrctrl_write(u8 c, u8 part, s16 inst, u16 cdoffs)
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{
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u32 v;
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v = omap4_cminst_read_inst_reg(part, inst, cdoffs + OMAP4_CM_CLKSTCTRL);
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v &= ~OMAP4430_CLKTRCTRL_MASK;
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v |= c << OMAP4430_CLKTRCTRL_SHIFT;
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omap4_cminst_write_inst_reg(v, part, inst, cdoffs + OMAP4_CM_CLKSTCTRL);
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}
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/**
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* omap4_cminst_is_clkdm_in_hwsup - is a clockdomain in hwsup idle mode?
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* @part: PRCM partition ID that the CM_CLKSTCTRL register exists in
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* @inst: CM instance register offset (*_INST macro)
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* @cdoffs: Clockdomain register offset (*_CDOFFS macro)
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*
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* Returns true if the clockdomain referred to by (@part, @inst, @cdoffs)
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* is in hardware-supervised idle mode, or 0 otherwise.
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*/
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bool omap4_cminst_is_clkdm_in_hwsup(u8 part, s16 inst, u16 cdoffs)
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{
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u32 v;
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v = omap4_cminst_read_inst_reg(part, inst, cdoffs + OMAP4_CM_CLKSTCTRL);
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v &= OMAP4430_CLKTRCTRL_MASK;
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v >>= OMAP4430_CLKTRCTRL_SHIFT;
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return (v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ? true : false;
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}
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/**
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* omap4_cminst_clkdm_enable_hwsup - put a clockdomain in hwsup-idle mode
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* @part: PRCM partition ID that the clockdomain registers exist in
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* @inst: CM instance register offset (*_INST macro)
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* @cdoffs: Clockdomain register offset (*_CDOFFS macro)
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*
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* Put a clockdomain referred to by (@part, @inst, @cdoffs) into
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* hardware-supervised idle mode. No return value.
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*/
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void omap4_cminst_clkdm_enable_hwsup(u8 part, s16 inst, u16 cdoffs)
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{
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_clktrctrl_write(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, part, inst, cdoffs);
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}
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/**
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* omap4_cminst_clkdm_disable_hwsup - put a clockdomain in swsup-idle mode
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* @part: PRCM partition ID that the clockdomain registers exist in
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* @inst: CM instance register offset (*_INST macro)
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* @cdoffs: Clockdomain register offset (*_CDOFFS macro)
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*
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* Put a clockdomain referred to by (@part, @inst, @cdoffs) into
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* software-supervised idle mode, i.e., controlled manually by the
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* Linux OMAP clockdomain code. No return value.
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*/
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void omap4_cminst_clkdm_disable_hwsup(u8 part, s16 inst, u16 cdoffs)
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{
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_clktrctrl_write(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, part, inst, cdoffs);
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}
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/**
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* omap4_cminst_clkdm_force_sleep - try to put a clockdomain into idle
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* @part: PRCM partition ID that the clockdomain registers exist in
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* @inst: CM instance register offset (*_INST macro)
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* @cdoffs: Clockdomain register offset (*_CDOFFS macro)
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*
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* Put a clockdomain referred to by (@part, @inst, @cdoffs) into idle
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* No return value.
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*/
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void omap4_cminst_clkdm_force_sleep(u8 part, s16 inst, u16 cdoffs)
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{
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_clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, part, inst, cdoffs);
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}
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/**
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* omap4_cminst_clkdm_force_sleep - try to take a clockdomain out of idle
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* @part: PRCM partition ID that the clockdomain registers exist in
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* @inst: CM instance register offset (*_INST macro)
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* @cdoffs: Clockdomain register offset (*_CDOFFS macro)
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*
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* Take a clockdomain referred to by (@part, @inst, @cdoffs) out of idle,
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* waking it up. No return value.
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*/
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void omap4_cminst_clkdm_force_wakeup(u8 part, s16 inst, u16 cdoffs)
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{
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_clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, part, inst, cdoffs);
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}
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/*
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*
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*/
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/**
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* omap4_cm_wait_module_ready - wait for a module to be in 'func' state
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* @clkctrl_reg: CLKCTRL module address
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*
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* Wait for the module IDLEST to be functional. If the idle state is in any
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* the non functional state (trans, idle or disabled), module and thus the
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* sysconfig cannot be accessed and will probably lead to an "imprecise
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* external abort"
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*
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* Module idle state:
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* 0x0 func: Module is fully functional, including OCP
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* 0x1 trans: Module is performing transition: wakeup, or sleep, or sleep
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* abortion
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* 0x2 idle: Module is in Idle mode (only OCP part). It is functional if
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* using separate functional clock
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* 0x3 disabled: Module is disabled and cannot be accessed
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*
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*/
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int omap4_cm_wait_module_ready(void __iomem *clkctrl_reg)
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{
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int i = 0;
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if (!clkctrl_reg)
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return 0;
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omap_test_timeout((
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((__raw_readl(clkctrl_reg) & OMAP4430_IDLEST_MASK) == 0) ||
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(((__raw_readl(clkctrl_reg) & OMAP4430_IDLEST_MASK) >>
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OMAP4430_IDLEST_SHIFT) == 0x2)),
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MAX_MODULE_READY_TIME, i);
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return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
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}
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