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On many MIPS systems the endianness of IP blocks is kept the same as that of the CPU by the hardware. This includes the system controllers on these systems which are controlled via syscon which uses the regmap API which used readl() and writel() to interact with the hardware, meaning that all writes are converted to little endian when writing to the hardware. This caused a bad interaction with the regmap core in big endian mode since it was not aware of the byte swapping and so ended up performing little endian writes. Unfortunately when this issue was noticed it was addressed by updating the DT for the affected devices to specify them as little endian. This happened to work since it resulted in two endianness swaps which cancelled each other out and gave little endian behaviour but meant that the DT was clearly not accurately describing the hardware. The intention of commit |
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| brcm | ||
| cavium-octeon | ||
| include | ||
| ingenic | ||
| lantiq | ||
| mti | ||
| netlogic | ||
| pic32 | ||
| qca | ||
| ralink | ||
| xilfpga | ||
| Makefile | ||