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https://github.com/edk2-porting/linux-next.git
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a1e537b3f0
This patch increases the timeout for PCI ELBI configuration to support low frequency Palladium images. Signed-off-by: Omer Shpigelman <oshpigelman@habana.ai> Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
417 lines
10 KiB
C
417 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright 2016-2019 HabanaLabs, Ltd.
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* All Rights Reserved.
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*/
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#include "habanalabs.h"
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#include "include/hw_ip/pci/pci_general.h"
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#include <linux/pci.h>
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#define HL_PLDM_PCI_ELBI_TIMEOUT_MSEC (HL_PCI_ELBI_TIMEOUT_MSEC * 10)
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/**
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* hl_pci_bars_map() - Map PCI BARs.
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* @hdev: Pointer to hl_device structure.
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* @bar_name: Array of BAR names.
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* @is_wc: Array with flag per BAR whether a write-combined mapping is needed.
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*
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* Request PCI regions and map them to kernel virtual addresses.
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*
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* Return: 0 on success, non-zero for failure.
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*/
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int hl_pci_bars_map(struct hl_device *hdev, const char * const name[3],
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bool is_wc[3])
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{
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struct pci_dev *pdev = hdev->pdev;
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int rc, i, bar;
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rc = pci_request_regions(pdev, HL_NAME);
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if (rc) {
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dev_err(hdev->dev, "Cannot obtain PCI resources\n");
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return rc;
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}
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for (i = 0 ; i < 3 ; i++) {
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bar = i * 2; /* 64-bit BARs */
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hdev->pcie_bar[bar] = is_wc[i] ?
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pci_ioremap_wc_bar(pdev, bar) :
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pci_ioremap_bar(pdev, bar);
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if (!hdev->pcie_bar[bar]) {
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dev_err(hdev->dev, "pci_ioremap%s_bar failed for %s\n",
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is_wc[i] ? "_wc" : "", name[i]);
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rc = -ENODEV;
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goto err;
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}
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}
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return 0;
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err:
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for (i = 2 ; i >= 0 ; i--) {
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bar = i * 2; /* 64-bit BARs */
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if (hdev->pcie_bar[bar])
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iounmap(hdev->pcie_bar[bar]);
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}
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pci_release_regions(pdev);
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return rc;
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}
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/*
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* hl_pci_bars_unmap() - Unmap PCI BARS.
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* @hdev: Pointer to hl_device structure.
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*
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* Release all PCI BARs and unmap their virtual addresses.
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*/
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static void hl_pci_bars_unmap(struct hl_device *hdev)
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{
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struct pci_dev *pdev = hdev->pdev;
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int i, bar;
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for (i = 2 ; i >= 0 ; i--) {
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bar = i * 2; /* 64-bit BARs */
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iounmap(hdev->pcie_bar[bar]);
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}
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pci_release_regions(pdev);
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}
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/*
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* hl_pci_elbi_write() - Write through the ELBI interface.
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* @hdev: Pointer to hl_device structure.
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*
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* Return: 0 on success, negative value for failure.
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*/
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static int hl_pci_elbi_write(struct hl_device *hdev, u64 addr, u32 data)
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{
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struct pci_dev *pdev = hdev->pdev;
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ktime_t timeout;
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u64 msec;
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u32 val;
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if (hdev->pldm)
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msec = HL_PLDM_PCI_ELBI_TIMEOUT_MSEC;
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else
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msec = HL_PCI_ELBI_TIMEOUT_MSEC;
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/* Clear previous status */
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pci_write_config_dword(pdev, mmPCI_CONFIG_ELBI_STS, 0);
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pci_write_config_dword(pdev, mmPCI_CONFIG_ELBI_ADDR, (u32) addr);
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pci_write_config_dword(pdev, mmPCI_CONFIG_ELBI_DATA, data);
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pci_write_config_dword(pdev, mmPCI_CONFIG_ELBI_CTRL,
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PCI_CONFIG_ELBI_CTRL_WRITE);
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timeout = ktime_add_ms(ktime_get(), msec);
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for (;;) {
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pci_read_config_dword(pdev, mmPCI_CONFIG_ELBI_STS, &val);
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if (val & PCI_CONFIG_ELBI_STS_MASK)
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break;
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if (ktime_compare(ktime_get(), timeout) > 0) {
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pci_read_config_dword(pdev, mmPCI_CONFIG_ELBI_STS,
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&val);
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break;
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}
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usleep_range(300, 500);
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}
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if ((val & PCI_CONFIG_ELBI_STS_MASK) == PCI_CONFIG_ELBI_STS_DONE)
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return 0;
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if (val & PCI_CONFIG_ELBI_STS_ERR) {
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dev_err(hdev->dev, "Error writing to ELBI\n");
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return -EIO;
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}
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if (!(val & PCI_CONFIG_ELBI_STS_MASK)) {
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dev_err(hdev->dev, "ELBI write didn't finish in time\n");
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return -EIO;
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}
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dev_err(hdev->dev, "ELBI write has undefined bits in status\n");
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return -EIO;
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}
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/**
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* hl_pci_iatu_write() - iatu write routine.
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* @hdev: Pointer to hl_device structure.
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*
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* Return: 0 on success, negative value for failure.
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*/
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int hl_pci_iatu_write(struct hl_device *hdev, u32 addr, u32 data)
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{
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struct asic_fixed_properties *prop = &hdev->asic_prop;
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u32 dbi_offset;
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int rc;
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dbi_offset = addr & 0xFFF;
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rc = hl_pci_elbi_write(hdev, prop->pcie_aux_dbi_reg_addr, 0x00300000);
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rc |= hl_pci_elbi_write(hdev, prop->pcie_dbi_base_address + dbi_offset,
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data);
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if (rc)
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return -EIO;
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return 0;
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}
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/*
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* hl_pci_reset_link_through_bridge() - Reset PCI link.
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* @hdev: Pointer to hl_device structure.
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*/
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static void hl_pci_reset_link_through_bridge(struct hl_device *hdev)
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{
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struct pci_dev *pdev = hdev->pdev;
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struct pci_dev *parent_port;
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u16 val;
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parent_port = pdev->bus->self;
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pci_read_config_word(parent_port, PCI_BRIDGE_CONTROL, &val);
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val |= PCI_BRIDGE_CTL_BUS_RESET;
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pci_write_config_word(parent_port, PCI_BRIDGE_CONTROL, val);
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ssleep(1);
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val &= ~(PCI_BRIDGE_CTL_BUS_RESET);
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pci_write_config_word(parent_port, PCI_BRIDGE_CONTROL, val);
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ssleep(3);
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}
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/**
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* hl_pci_set_dram_bar_base() - Set DDR BAR to map specific device address.
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* @hdev: Pointer to hl_device structure.
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* @inbound_region: Inbound region number.
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* @bar: PCI BAR number.
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* @addr: Address in DRAM. Must be aligned to DRAM bar size.
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*
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* Configure the iATU so that the DRAM bar will start at the specified address.
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*
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* Return: 0 on success, negative value for failure.
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*/
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int hl_pci_set_dram_bar_base(struct hl_device *hdev, u8 inbound_region, u8 bar,
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u64 addr)
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{
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struct asic_fixed_properties *prop = &hdev->asic_prop;
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u32 offset;
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int rc;
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switch (inbound_region) {
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case 0:
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offset = 0x100;
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break;
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case 1:
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offset = 0x300;
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break;
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case 2:
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offset = 0x500;
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break;
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default:
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dev_err(hdev->dev, "Invalid inbound region %d\n",
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inbound_region);
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return -EINVAL;
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}
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if (bar != 0 && bar != 2 && bar != 4) {
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dev_err(hdev->dev, "Invalid PCI BAR %d\n", bar);
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return -EINVAL;
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}
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/* Point to the specified address */
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rc = hl_pci_iatu_write(hdev, offset + 0x14, lower_32_bits(addr));
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rc |= hl_pci_iatu_write(hdev, offset + 0x18, upper_32_bits(addr));
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rc |= hl_pci_iatu_write(hdev, offset + 0x0, 0);
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/* Enable + BAR match + match enable + BAR number */
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rc |= hl_pci_iatu_write(hdev, offset + 0x4, 0xC0080000 | (bar << 8));
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/* Return the DBI window to the default location */
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rc |= hl_pci_elbi_write(hdev, prop->pcie_aux_dbi_reg_addr, 0);
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rc |= hl_pci_elbi_write(hdev, prop->pcie_aux_dbi_reg_addr + 4, 0);
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if (rc)
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dev_err(hdev->dev, "failed to map DRAM bar to 0x%08llx\n",
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addr);
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return rc;
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}
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/**
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* hl_pci_init_iatu() - Initialize the iATU unit inside the PCI controller.
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* @hdev: Pointer to hl_device structure.
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* @sram_base_address: SRAM base address.
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* @dram_base_address: DRAM base address.
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* @host_phys_base_address: Base physical address of host memory for device
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* transactions.
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* @host_phys_size: Size of host memory for device transactions.
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*
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* This is needed in case the firmware doesn't initialize the iATU.
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*
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* Return: 0 on success, negative value for failure.
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*/
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int hl_pci_init_iatu(struct hl_device *hdev, u64 sram_base_address,
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u64 dram_base_address, u64 host_phys_base_address,
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u64 host_phys_size)
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{
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struct asic_fixed_properties *prop = &hdev->asic_prop;
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u64 host_phys_end_addr;
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int rc = 0;
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/* Inbound Region 0 - Bar 0 - Point to SRAM base address */
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rc = hl_pci_iatu_write(hdev, 0x114, lower_32_bits(sram_base_address));
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rc |= hl_pci_iatu_write(hdev, 0x118, upper_32_bits(sram_base_address));
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rc |= hl_pci_iatu_write(hdev, 0x100, 0);
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/* Enable + Bar match + match enable */
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rc |= hl_pci_iatu_write(hdev, 0x104, 0xC0080000);
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/* Point to DRAM */
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if (!hdev->asic_funcs->set_dram_bar_base)
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return -EINVAL;
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if (hdev->asic_funcs->set_dram_bar_base(hdev, dram_base_address) ==
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U64_MAX)
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return -EIO;
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/* Outbound Region 0 - Point to Host */
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host_phys_end_addr = host_phys_base_address + host_phys_size - 1;
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rc |= hl_pci_iatu_write(hdev, 0x008,
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lower_32_bits(host_phys_base_address));
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rc |= hl_pci_iatu_write(hdev, 0x00C,
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upper_32_bits(host_phys_base_address));
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rc |= hl_pci_iatu_write(hdev, 0x010, lower_32_bits(host_phys_end_addr));
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rc |= hl_pci_iatu_write(hdev, 0x014, 0);
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rc |= hl_pci_iatu_write(hdev, 0x018, 0);
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rc |= hl_pci_iatu_write(hdev, 0x020, upper_32_bits(host_phys_end_addr));
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/* Increase region size */
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rc |= hl_pci_iatu_write(hdev, 0x000, 0x00002000);
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/* Enable */
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rc |= hl_pci_iatu_write(hdev, 0x004, 0x80000000);
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/* Return the DBI window to the default location */
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rc |= hl_pci_elbi_write(hdev, prop->pcie_aux_dbi_reg_addr, 0);
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rc |= hl_pci_elbi_write(hdev, prop->pcie_aux_dbi_reg_addr + 4, 0);
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if (rc)
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return -EIO;
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return 0;
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}
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/**
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* hl_pci_set_dma_mask() - Set DMA masks for the device.
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* @hdev: Pointer to hl_device structure.
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* @dma_mask: number of bits for the requested dma mask.
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*
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* This function sets the DMA masks (regular and consistent) for a specified
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* value. If it doesn't succeed, it tries to set it to a fall-back value
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*
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* Return: 0 on success, non-zero for failure.
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*/
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int hl_pci_set_dma_mask(struct hl_device *hdev, u8 dma_mask)
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{
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struct pci_dev *pdev = hdev->pdev;
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int rc;
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/* set DMA mask */
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rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(dma_mask));
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if (rc) {
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dev_warn(hdev->dev,
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"Failed to set pci dma mask to %d bits, error %d\n",
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dma_mask, rc);
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dma_mask = hdev->dma_mask;
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rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(dma_mask));
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if (rc) {
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dev_err(hdev->dev,
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"Failed to set pci dma mask to %d bits, error %d\n",
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dma_mask, rc);
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return rc;
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}
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}
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/*
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* We managed to set the dma mask, so update the dma mask field. If
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* the set to the coherent mask will fail with that mask, we will
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* fail the entire function
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*/
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hdev->dma_mask = dma_mask;
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rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(dma_mask));
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if (rc) {
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dev_err(hdev->dev,
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"Failed to set pci consistent dma mask to %d bits, error %d\n",
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dma_mask, rc);
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return rc;
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}
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return 0;
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}
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/**
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* hl_pci_init() - PCI initialization code.
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* @hdev: Pointer to hl_device structure.
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* @dma_mask: number of bits for the requested dma mask.
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*
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* Set DMA masks, initialize the PCI controller and map the PCI BARs.
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*
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* Return: 0 on success, non-zero for failure.
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*/
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int hl_pci_init(struct hl_device *hdev, u8 dma_mask)
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{
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struct pci_dev *pdev = hdev->pdev;
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int rc;
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rc = hl_pci_set_dma_mask(hdev, dma_mask);
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if (rc)
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return rc;
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if (hdev->reset_pcilink)
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hl_pci_reset_link_through_bridge(hdev);
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rc = pci_enable_device_mem(pdev);
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if (rc) {
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dev_err(hdev->dev, "can't enable PCI device\n");
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return rc;
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}
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pci_set_master(pdev);
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rc = hdev->asic_funcs->init_iatu(hdev);
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if (rc) {
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dev_err(hdev->dev, "Failed to initialize iATU\n");
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goto disable_device;
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}
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rc = hdev->asic_funcs->pci_bars_map(hdev);
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if (rc) {
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dev_err(hdev->dev, "Failed to initialize PCI BARs\n");
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goto disable_device;
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}
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return 0;
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disable_device:
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pci_clear_master(pdev);
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pci_disable_device(pdev);
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return rc;
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}
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/**
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* hl_fw_fini() - PCI finalization code.
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* @hdev: Pointer to hl_device structure
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*
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* Unmap PCI bars and disable PCI device.
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*/
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void hl_pci_fini(struct hl_device *hdev)
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{
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hl_pci_bars_unmap(hdev);
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pci_clear_master(hdev->pdev);
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pci_disable_device(hdev->pdev);
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}
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