mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-21 19:53:59 +08:00
3a044178cc
Even on x86-64, I've found the need to break up a readq() into 2 readl() calls. According to the Intel datasheet for the E3-1200 processor: " Software must not access B0/D0/F0 32-bit memory-mapped registers with requests that cross a DW boundary. " (http://www.intel.com/content/www/us/en/processors/xeon/xeon-e3-1200-family-vol-2-datasheet.html p. 16) I can confirm this is true via several hard machine lockups. Thus, add explicit hi_lo_[readq|write]_q and lo_hi_[read|write]_q so that these uses are spelled out. Signed-off-by: Jason Baron <jbaron@akamai.com> Link: http://lkml.kernel.org/r/281f09da7ad01e5cea99737ec34d2399bdbbbf63.1403818526.git.jbaron@akamai.com Signed-off-by: Borislav Petkov <bp@suse.de>
33 lines
604 B
C
33 lines
604 B
C
#ifndef _ASM_IO_64_NONATOMIC_LO_HI_H_
|
|
#define _ASM_IO_64_NONATOMIC_LO_HI_H_
|
|
|
|
#include <linux/io.h>
|
|
#include <asm-generic/int-ll64.h>
|
|
|
|
static inline __u64 lo_hi_readq(const volatile void __iomem *addr)
|
|
{
|
|
const volatile u32 __iomem *p = addr;
|
|
u32 low, high;
|
|
|
|
low = readl(p);
|
|
high = readl(p + 1);
|
|
|
|
return low + ((u64)high << 32);
|
|
}
|
|
|
|
static inline void lo_hi_writeq(__u64 val, volatile void __iomem *addr)
|
|
{
|
|
writel(val, addr);
|
|
writel(val >> 32, addr + 4);
|
|
}
|
|
|
|
#ifndef readq
|
|
#define readq lo_hi_readq
|
|
#endif
|
|
|
|
#ifndef writeq
|
|
#define writeq lo_hi_writeq
|
|
#endif
|
|
|
|
#endif /* _ASM_IO_64_NONATOMIC_LO_HI_H_ */
|