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Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation version 2 of the license extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 315 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Armijn Hemel <armijn@tjaldur.nl> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190531190115.503150771@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
147 lines
3.1 KiB
C
147 lines
3.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* CPPC (Collaborative Processor Performance Control) methods used
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* by CPUfreq drivers.
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*
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* (C) Copyright 2014, 2015 Linaro Ltd.
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* Author: Ashwin Chaugule <ashwin.chaugule@linaro.org>
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*/
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#ifndef _CPPC_ACPI_H
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#define _CPPC_ACPI_H
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#include <linux/acpi.h>
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#include <linux/types.h>
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#include <acpi/pcc.h>
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#include <acpi/processor.h>
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/* Support CPPCv2 and CPPCv3 */
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#define CPPC_V2_REV 2
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#define CPPC_V3_REV 3
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#define CPPC_V2_NUM_ENT 21
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#define CPPC_V3_NUM_ENT 23
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#define PCC_CMD_COMPLETE_MASK (1 << 0)
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#define PCC_ERROR_MASK (1 << 2)
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#define MAX_CPC_REG_ENT 21
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/* CPPC specific PCC commands. */
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#define CMD_READ 0
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#define CMD_WRITE 1
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/* Each register has the folowing format. */
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struct cpc_reg {
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u8 descriptor;
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u16 length;
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u8 space_id;
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u8 bit_width;
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u8 bit_offset;
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u8 access_width;
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u64 __iomem address;
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} __packed;
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/*
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* Each entry in the CPC table is either
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* of type ACPI_TYPE_BUFFER or
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* ACPI_TYPE_INTEGER.
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*/
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struct cpc_register_resource {
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acpi_object_type type;
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u64 __iomem *sys_mem_vaddr;
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union {
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struct cpc_reg reg;
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u64 int_value;
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} cpc_entry;
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};
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/* Container to hold the CPC details for each CPU */
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struct cpc_desc {
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int num_entries;
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int version;
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int cpu_id;
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int write_cmd_status;
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int write_cmd_id;
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struct cpc_register_resource cpc_regs[MAX_CPC_REG_ENT];
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struct acpi_psd_package domain_info;
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struct kobject kobj;
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};
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/* These are indexes into the per-cpu cpc_regs[]. Order is important. */
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enum cppc_regs {
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HIGHEST_PERF,
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NOMINAL_PERF,
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LOW_NON_LINEAR_PERF,
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LOWEST_PERF,
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GUARANTEED_PERF,
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DESIRED_PERF,
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MIN_PERF,
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MAX_PERF,
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PERF_REDUC_TOLERANCE,
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TIME_WINDOW,
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CTR_WRAP_TIME,
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REFERENCE_CTR,
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DELIVERED_CTR,
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PERF_LIMITED,
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ENABLE,
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AUTO_SEL_ENABLE,
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AUTO_ACT_WINDOW,
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ENERGY_PERF,
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REFERENCE_PERF,
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LOWEST_FREQ,
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NOMINAL_FREQ,
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};
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/*
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* Categorization of registers as described
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* in the ACPI v.5.1 spec.
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* XXX: Only filling up ones which are used by governors
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* today.
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*/
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struct cppc_perf_caps {
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u32 guaranteed_perf;
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u32 highest_perf;
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u32 nominal_perf;
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u32 lowest_perf;
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u32 lowest_nonlinear_perf;
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u32 lowest_freq;
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u32 nominal_freq;
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};
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struct cppc_perf_ctrls {
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u32 max_perf;
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u32 min_perf;
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u32 desired_perf;
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};
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struct cppc_perf_fb_ctrs {
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u64 reference;
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u64 delivered;
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u64 reference_perf;
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u64 wraparound_time;
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};
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/* Per CPU container for runtime CPPC management. */
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struct cppc_cpudata {
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int cpu;
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struct cppc_perf_caps perf_caps;
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struct cppc_perf_ctrls perf_ctrls;
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struct cppc_perf_fb_ctrs perf_fb_ctrs;
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struct cpufreq_policy *cur_policy;
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unsigned int shared_type;
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cpumask_var_t shared_cpu_map;
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};
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extern int cppc_get_desired_perf(int cpunum, u64 *desired_perf);
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extern int cppc_get_perf_ctrs(int cpu, struct cppc_perf_fb_ctrs *perf_fb_ctrs);
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extern int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls);
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extern int cppc_get_perf_caps(int cpu, struct cppc_perf_caps *caps);
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extern int acpi_get_psd_map(struct cppc_cpudata **);
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extern unsigned int cppc_get_transition_latency(int cpu);
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extern bool cpc_ffh_supported(void);
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extern int cpc_read_ffh(int cpunum, struct cpc_reg *reg, u64 *val);
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extern int cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val);
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#endif /* _CPPC_ACPI_H*/
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