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862f0eea38
Tegra124 only has 4 UARTs. Parts of the documentation hint at a fifth UART, but this appears to be left-over from earlier SoC documentation. Remove the non-existent DT node for UART5. Cc: <stable@vger.kernel.org> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
726 lines
21 KiB
Plaintext
726 lines
21 KiB
Plaintext
#include <dt-bindings/clock/tegra124-car.h>
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#include <dt-bindings/gpio/tegra-gpio.h>
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#include <dt-bindings/pinctrl/pinctrl-tegra.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include "skeleton.dtsi"
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/ {
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compatible = "nvidia,tegra124";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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host1x@0,50000000 {
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compatible = "nvidia,tegra124-host1x", "simple-bus";
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reg = <0x0 0x50000000 0x0 0x00034000>;
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interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
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<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
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clocks = <&tegra_car TEGRA124_CLK_HOST1X>;
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resets = <&tegra_car 28>;
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reset-names = "host1x";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0 0x54000000 0 0x54000000 0 0x01000000>;
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dc@0,54200000 {
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compatible = "nvidia,tegra124-dc";
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reg = <0x0 0x54200000 0x0 0x00040000>;
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interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA124_CLK_DISP1>,
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<&tegra_car TEGRA124_CLK_PLL_P>;
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clock-names = "dc", "parent";
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resets = <&tegra_car 27>;
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reset-names = "dc";
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nvidia,head = <0>;
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};
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dc@0,54240000 {
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compatible = "nvidia,tegra124-dc";
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reg = <0x0 0x54240000 0x0 0x00040000>;
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interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA124_CLK_DISP2>,
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<&tegra_car TEGRA124_CLK_PLL_P>;
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clock-names = "dc", "parent";
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resets = <&tegra_car 26>;
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reset-names = "dc";
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nvidia,head = <1>;
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};
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sor@0,54540000 {
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compatible = "nvidia,tegra124-sor";
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reg = <0x0 0x54540000 0x0 0x00040000>;
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interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA124_CLK_SOR0>,
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<&tegra_car TEGRA124_CLK_PLL_D_OUT0>,
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<&tegra_car TEGRA124_CLK_PLL_DP>,
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<&tegra_car TEGRA124_CLK_CLK_M>;
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clock-names = "sor", "parent", "dp", "safe";
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resets = <&tegra_car 182>;
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reset-names = "sor";
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status = "disabled";
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};
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dpaux@0,545c0000 {
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compatible = "nvidia,tegra124-dpaux";
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reg = <0x0 0x545c0000 0x0 0x00040000>;
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interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA124_CLK_DPAUX>,
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<&tegra_car TEGRA124_CLK_PLL_DP>;
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clock-names = "dpaux", "parent";
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resets = <&tegra_car 181>;
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reset-names = "dpaux";
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status = "disabled";
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};
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};
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gic: interrupt-controller@0,50041000 {
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compatible = "arm,cortex-a15-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x0 0x50041000 0x0 0x1000>,
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<0x0 0x50042000 0x0 0x1000>,
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<0x0 0x50044000 0x0 0x2000>,
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<0x0 0x50046000 0x0 0x2000>;
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interrupts = <GIC_PPI 9
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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timer@0,60005000 {
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compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer";
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reg = <0x0 0x60005000 0x0 0x400>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA124_CLK_TIMER>;
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};
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tegra_car: clock@0,60006000 {
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compatible = "nvidia,tegra124-car";
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reg = <0x0 0x60006000 0x0 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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gpio: gpio@0,6000d000 {
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compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
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reg = <0x0 0x6000d000 0x0 0x1000>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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#interrupt-cells = <2>;
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interrupt-controller;
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};
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apbdma: dma@0,60020000 {
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compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
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reg = <0x0 0x60020000 0x0 0x1400>;
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interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA124_CLK_APBDMA>;
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resets = <&tegra_car 34>;
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reset-names = "dma";
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#dma-cells = <1>;
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};
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pinmux: pinmux@0,70000868 {
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compatible = "nvidia,tegra124-pinmux";
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reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
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<0x0 0x70003000 0x0 0x434>; /* Mux registers */
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};
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/*
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* There are two serial driver i.e. 8250 based simple serial
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* driver and APB DMA based serial driver for higher baudrate
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* and performace. To enable the 8250 based driver, the compatible
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* is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
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* the APB DMA based serial driver, the comptible is
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* "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
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*/
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serial@0,70006000 {
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compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
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reg = <0x0 0x70006000 0x0 0x40>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA124_CLK_UARTA>;
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resets = <&tegra_car 6>;
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reset-names = "serial";
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dmas = <&apbdma 8>, <&apbdma 8>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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serial@0,70006040 {
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compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
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reg = <0x0 0x70006040 0x0 0x40>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA124_CLK_UARTB>;
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resets = <&tegra_car 7>;
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reset-names = "serial";
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dmas = <&apbdma 9>, <&apbdma 9>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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serial@0,70006200 {
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compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
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reg = <0x0 0x70006200 0x0 0x40>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA124_CLK_UARTC>;
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resets = <&tegra_car 55>;
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reset-names = "serial";
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dmas = <&apbdma 10>, <&apbdma 10>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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serial@0,70006300 {
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compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
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reg = <0x0 0x70006300 0x0 0x40>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA124_CLK_UARTD>;
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resets = <&tegra_car 65>;
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reset-names = "serial";
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dmas = <&apbdma 19>, <&apbdma 19>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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pwm@0,7000a000 {
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compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
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reg = <0x0 0x7000a000 0x0 0x100>;
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#pwm-cells = <2>;
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clocks = <&tegra_car TEGRA124_CLK_PWM>;
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resets = <&tegra_car 17>;
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reset-names = "pwm";
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status = "disabled";
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};
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i2c@0,7000c000 {
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compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
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reg = <0x0 0x7000c000 0x0 0x100>;
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interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&tegra_car TEGRA124_CLK_I2C1>;
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clock-names = "div-clk";
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resets = <&tegra_car 12>;
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reset-names = "i2c";
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dmas = <&apbdma 21>, <&apbdma 21>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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i2c@0,7000c400 {
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compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
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reg = <0x0 0x7000c400 0x0 0x100>;
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interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&tegra_car TEGRA124_CLK_I2C2>;
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clock-names = "div-clk";
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resets = <&tegra_car 54>;
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reset-names = "i2c";
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dmas = <&apbdma 22>, <&apbdma 22>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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i2c@0,7000c500 {
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compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
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reg = <0x0 0x7000c500 0x0 0x100>;
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interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&tegra_car TEGRA124_CLK_I2C3>;
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clock-names = "div-clk";
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resets = <&tegra_car 67>;
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reset-names = "i2c";
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dmas = <&apbdma 23>, <&apbdma 23>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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i2c@0,7000c700 {
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compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
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reg = <0x0 0x7000c700 0x0 0x100>;
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interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&tegra_car TEGRA124_CLK_I2C4>;
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clock-names = "div-clk";
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resets = <&tegra_car 103>;
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reset-names = "i2c";
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dmas = <&apbdma 26>, <&apbdma 26>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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i2c@0,7000d000 {
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compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
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reg = <0x0 0x7000d000 0x0 0x100>;
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interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&tegra_car TEGRA124_CLK_I2C5>;
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clock-names = "div-clk";
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resets = <&tegra_car 47>;
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reset-names = "i2c";
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dmas = <&apbdma 24>, <&apbdma 24>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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i2c@0,7000d100 {
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compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
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reg = <0x0 0x7000d100 0x0 0x100>;
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interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&tegra_car TEGRA124_CLK_I2C6>;
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clock-names = "div-clk";
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resets = <&tegra_car 166>;
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reset-names = "i2c";
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dmas = <&apbdma 30>, <&apbdma 30>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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spi@0,7000d400 {
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compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
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reg = <0x0 0x7000d400 0x0 0x200>;
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interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&tegra_car TEGRA124_CLK_SBC1>;
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clock-names = "spi";
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resets = <&tegra_car 41>;
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reset-names = "spi";
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dmas = <&apbdma 15>, <&apbdma 15>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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spi@0,7000d600 {
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compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
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reg = <0x0 0x7000d600 0x0 0x200>;
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interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&tegra_car TEGRA124_CLK_SBC2>;
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clock-names = "spi";
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resets = <&tegra_car 44>;
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reset-names = "spi";
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dmas = <&apbdma 16>, <&apbdma 16>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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spi@0,7000d800 {
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compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
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reg = <0x0 0x7000d800 0x0 0x200>;
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interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&tegra_car TEGRA124_CLK_SBC3>;
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clock-names = "spi";
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resets = <&tegra_car 46>;
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reset-names = "spi";
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dmas = <&apbdma 17>, <&apbdma 17>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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spi@0,7000da00 {
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compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
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reg = <0x0 0x7000da00 0x0 0x200>;
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interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&tegra_car TEGRA124_CLK_SBC4>;
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clock-names = "spi";
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resets = <&tegra_car 68>;
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reset-names = "spi";
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dmas = <&apbdma 18>, <&apbdma 18>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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spi@0,7000dc00 {
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compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
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reg = <0x0 0x7000dc00 0x0 0x200>;
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interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&tegra_car TEGRA124_CLK_SBC5>;
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clock-names = "spi";
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resets = <&tegra_car 104>;
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reset-names = "spi";
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dmas = <&apbdma 27>, <&apbdma 27>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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spi@0,7000de00 {
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compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
|
|
reg = <0x0 0x7000de00 0x0 0x200>;
|
|
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&tegra_car TEGRA124_CLK_SBC6>;
|
|
clock-names = "spi";
|
|
resets = <&tegra_car 105>;
|
|
reset-names = "spi";
|
|
dmas = <&apbdma 28>, <&apbdma 28>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
rtc@0,7000e000 {
|
|
compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc";
|
|
reg = <0x0 0x7000e000 0x0 0x100>;
|
|
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&tegra_car TEGRA124_CLK_RTC>;
|
|
};
|
|
|
|
pmc@0,7000e400 {
|
|
compatible = "nvidia,tegra124-pmc";
|
|
reg = <0x0 0x7000e400 0x0 0x400>;
|
|
clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
|
|
clock-names = "pclk", "clk32k_in";
|
|
};
|
|
|
|
sdhci@0,700b0000 {
|
|
compatible = "nvidia,tegra124-sdhci";
|
|
reg = <0x0 0x700b0000 0x0 0x200>;
|
|
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&tegra_car TEGRA124_CLK_SDMMC1>;
|
|
resets = <&tegra_car 14>;
|
|
reset-names = "sdhci";
|
|
status = "disabled";
|
|
};
|
|
|
|
sdhci@0,700b0200 {
|
|
compatible = "nvidia,tegra124-sdhci";
|
|
reg = <0x0 0x700b0200 0x0 0x200>;
|
|
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&tegra_car TEGRA124_CLK_SDMMC2>;
|
|
resets = <&tegra_car 9>;
|
|
reset-names = "sdhci";
|
|
status = "disabled";
|
|
};
|
|
|
|
sdhci@0,700b0400 {
|
|
compatible = "nvidia,tegra124-sdhci";
|
|
reg = <0x0 0x700b0400 0x0 0x200>;
|
|
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&tegra_car TEGRA124_CLK_SDMMC3>;
|
|
resets = <&tegra_car 69>;
|
|
reset-names = "sdhci";
|
|
status = "disabled";
|
|
};
|
|
|
|
sdhci@0,700b0600 {
|
|
compatible = "nvidia,tegra124-sdhci";
|
|
reg = <0x0 0x700b0600 0x0 0x200>;
|
|
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&tegra_car TEGRA124_CLK_SDMMC4>;
|
|
resets = <&tegra_car 15>;
|
|
reset-names = "sdhci";
|
|
status = "disabled";
|
|
};
|
|
|
|
ahub@0,70300000 {
|
|
compatible = "nvidia,tegra124-ahub";
|
|
reg = <0x0 0x70300000 0x0 0x200>,
|
|
<0x0 0x70300800 0x0 0x800>,
|
|
<0x0 0x70300200 0x0 0x600>;
|
|
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>,
|
|
<&tegra_car TEGRA124_CLK_APBIF>;
|
|
clock-names = "d_audio", "apbif";
|
|
resets = <&tegra_car 106>, /* d_audio */
|
|
<&tegra_car 107>, /* apbif */
|
|
<&tegra_car 30>, /* i2s0 */
|
|
<&tegra_car 11>, /* i2s1 */
|
|
<&tegra_car 18>, /* i2s2 */
|
|
<&tegra_car 101>, /* i2s3 */
|
|
<&tegra_car 102>, /* i2s4 */
|
|
<&tegra_car 108>, /* dam0 */
|
|
<&tegra_car 109>, /* dam1 */
|
|
<&tegra_car 110>, /* dam2 */
|
|
<&tegra_car 10>, /* spdif */
|
|
<&tegra_car 153>, /* amx */
|
|
<&tegra_car 185>, /* amx1 */
|
|
<&tegra_car 154>, /* adx */
|
|
<&tegra_car 180>, /* adx1 */
|
|
<&tegra_car 186>, /* afc0 */
|
|
<&tegra_car 187>, /* afc1 */
|
|
<&tegra_car 188>, /* afc2 */
|
|
<&tegra_car 189>, /* afc3 */
|
|
<&tegra_car 190>, /* afc4 */
|
|
<&tegra_car 191>; /* afc5 */
|
|
reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
|
|
"i2s3", "i2s4", "dam0", "dam1", "dam2",
|
|
"spdif", "amx", "amx1", "adx", "adx1",
|
|
"afc0", "afc1", "afc2", "afc3", "afc4", "afc5";
|
|
dmas = <&apbdma 1>, <&apbdma 1>,
|
|
<&apbdma 2>, <&apbdma 2>,
|
|
<&apbdma 3>, <&apbdma 3>,
|
|
<&apbdma 4>, <&apbdma 4>,
|
|
<&apbdma 6>, <&apbdma 6>,
|
|
<&apbdma 7>, <&apbdma 7>,
|
|
<&apbdma 12>, <&apbdma 12>,
|
|
<&apbdma 13>, <&apbdma 13>,
|
|
<&apbdma 14>, <&apbdma 14>,
|
|
<&apbdma 29>, <&apbdma 29>;
|
|
dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
|
|
"rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
|
|
"rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
|
|
"rx9", "tx9";
|
|
ranges;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
|
|
tegra_i2s0: i2s@0,70301000 {
|
|
compatible = "nvidia,tegra124-i2s";
|
|
reg = <0x0 0x70301000 0x0 0x100>;
|
|
nvidia,ahub-cif-ids = <4 4>;
|
|
clocks = <&tegra_car TEGRA124_CLK_I2S0>;
|
|
resets = <&tegra_car 30>;
|
|
reset-names = "i2s";
|
|
status = "disabled";
|
|
};
|
|
|
|
tegra_i2s1: i2s@0,70301100 {
|
|
compatible = "nvidia,tegra124-i2s";
|
|
reg = <0x0 0x70301100 0x0 0x100>;
|
|
nvidia,ahub-cif-ids = <5 5>;
|
|
clocks = <&tegra_car TEGRA124_CLK_I2S1>;
|
|
resets = <&tegra_car 11>;
|
|
reset-names = "i2s";
|
|
status = "disabled";
|
|
};
|
|
|
|
tegra_i2s2: i2s@0,70301200 {
|
|
compatible = "nvidia,tegra124-i2s";
|
|
reg = <0x0 0x70301200 0x0 0x100>;
|
|
nvidia,ahub-cif-ids = <6 6>;
|
|
clocks = <&tegra_car TEGRA124_CLK_I2S2>;
|
|
resets = <&tegra_car 18>;
|
|
reset-names = "i2s";
|
|
status = "disabled";
|
|
};
|
|
|
|
tegra_i2s3: i2s@0,70301300 {
|
|
compatible = "nvidia,tegra124-i2s";
|
|
reg = <0x0 0x70301300 0x0 0x100>;
|
|
nvidia,ahub-cif-ids = <7 7>;
|
|
clocks = <&tegra_car TEGRA124_CLK_I2S3>;
|
|
resets = <&tegra_car 101>;
|
|
reset-names = "i2s";
|
|
status = "disabled";
|
|
};
|
|
|
|
tegra_i2s4: i2s@0,70301400 {
|
|
compatible = "nvidia,tegra124-i2s";
|
|
reg = <0x0 0x70301400 0x0 0x100>;
|
|
nvidia,ahub-cif-ids = <8 8>;
|
|
clocks = <&tegra_car TEGRA124_CLK_I2S4>;
|
|
resets = <&tegra_car 102>;
|
|
reset-names = "i2s";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
usb@0,7d000000 {
|
|
compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
|
|
reg = <0x0 0x7d000000 0x0 0x4000>;
|
|
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
|
phy_type = "utmi";
|
|
clocks = <&tegra_car TEGRA124_CLK_USBD>;
|
|
resets = <&tegra_car 22>;
|
|
reset-names = "usb";
|
|
nvidia,phy = <&phy1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
phy1: usb-phy@0,7d000000 {
|
|
compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
|
|
reg = <0x0 0x7d000000 0x0 0x4000>,
|
|
<0x0 0x7d000000 0x0 0x4000>;
|
|
phy_type = "utmi";
|
|
clocks = <&tegra_car TEGRA124_CLK_USBD>,
|
|
<&tegra_car TEGRA124_CLK_PLL_U>,
|
|
<&tegra_car TEGRA124_CLK_USBD>;
|
|
clock-names = "reg", "pll_u", "utmi-pads";
|
|
nvidia,hssync-start-delay = <0>;
|
|
nvidia,idle-wait-delay = <17>;
|
|
nvidia,elastic-limit = <16>;
|
|
nvidia,term-range-adj = <6>;
|
|
nvidia,xcvr-setup = <9>;
|
|
nvidia,xcvr-lsfslew = <0>;
|
|
nvidia,xcvr-lsrslew = <3>;
|
|
nvidia,hssquelch-level = <2>;
|
|
nvidia,hsdiscon-level = <5>;
|
|
nvidia,xcvr-hsslew = <12>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usb@0,7d004000 {
|
|
compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
|
|
reg = <0x0 0x7d004000 0x0 0x4000>;
|
|
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
|
|
phy_type = "utmi";
|
|
clocks = <&tegra_car TEGRA124_CLK_USB2>;
|
|
resets = <&tegra_car 58>;
|
|
reset-names = "usb";
|
|
nvidia,phy = <&phy2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
phy2: usb-phy@0,7d004000 {
|
|
compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
|
|
reg = <0x0 0x7d004000 0x0 0x4000>,
|
|
<0x0 0x7d000000 0x0 0x4000>;
|
|
phy_type = "utmi";
|
|
clocks = <&tegra_car TEGRA124_CLK_USB2>,
|
|
<&tegra_car TEGRA124_CLK_PLL_U>,
|
|
<&tegra_car TEGRA124_CLK_USBD>;
|
|
clock-names = "reg", "pll_u", "utmi-pads";
|
|
nvidia,hssync-start-delay = <0>;
|
|
nvidia,idle-wait-delay = <17>;
|
|
nvidia,elastic-limit = <16>;
|
|
nvidia,term-range-adj = <6>;
|
|
nvidia,xcvr-setup = <9>;
|
|
nvidia,xcvr-lsfslew = <0>;
|
|
nvidia,xcvr-lsrslew = <3>;
|
|
nvidia,hssquelch-level = <2>;
|
|
nvidia,hsdiscon-level = <5>;
|
|
nvidia,xcvr-hsslew = <12>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usb@0,7d008000 {
|
|
compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
|
|
reg = <0x0 0x7d008000 0x0 0x4000>;
|
|
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
|
|
phy_type = "utmi";
|
|
clocks = <&tegra_car TEGRA124_CLK_USB3>;
|
|
resets = <&tegra_car 59>;
|
|
reset-names = "usb";
|
|
nvidia,phy = <&phy3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
phy3: usb-phy@0,7d008000 {
|
|
compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
|
|
reg = <0x0 0x7d008000 0x0 0x4000>,
|
|
<0x0 0x7d000000 0x0 0x4000>;
|
|
phy_type = "utmi";
|
|
clocks = <&tegra_car TEGRA124_CLK_USB3>,
|
|
<&tegra_car TEGRA124_CLK_PLL_U>,
|
|
<&tegra_car TEGRA124_CLK_USBD>;
|
|
clock-names = "reg", "pll_u", "utmi-pads";
|
|
nvidia,hssync-start-delay = <0>;
|
|
nvidia,idle-wait-delay = <17>;
|
|
nvidia,elastic-limit = <16>;
|
|
nvidia,term-range-adj = <6>;
|
|
nvidia,xcvr-setup = <9>;
|
|
nvidia,xcvr-lsfslew = <0>;
|
|
nvidia,xcvr-lsrslew = <3>;
|
|
nvidia,hssquelch-level = <2>;
|
|
nvidia,hsdiscon-level = <5>;
|
|
nvidia,xcvr-hsslew = <12>;
|
|
status = "disabled";
|
|
};
|
|
|
|
cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
cpu@0 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a15";
|
|
reg = <0>;
|
|
};
|
|
|
|
cpu@1 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a15";
|
|
reg = <1>;
|
|
};
|
|
|
|
cpu@2 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a15";
|
|
reg = <2>;
|
|
};
|
|
|
|
cpu@3 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a15";
|
|
reg = <3>;
|
|
};
|
|
};
|
|
|
|
timer {
|
|
compatible = "arm,armv7-timer";
|
|
interrupts = <GIC_PPI 13
|
|
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 14
|
|
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 11
|
|
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 10
|
|
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
|
};
|
|
};
|