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f729dd554e
Latest Renesas Chip has some SDHI channels and the WP pin availability depends on its channel or HW implementation. Thus, this patch decides new policy whch indicates WP is disabled as default. But, we can use wp-gpios property to enable it as other method. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
113 lines
2.3 KiB
Plaintext
113 lines
2.3 KiB
Plaintext
/*
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* Reference Device Tree Source for the Bock-W board
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*
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* Copyright (C) 2013 Renesas Solutions Corp.
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* Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
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*
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* based on r8a7779
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*
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* Copyright (C) 2013 Renesas Solutions Corp.
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* Copyright (C) 2013 Simon Horman
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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/dts-v1/;
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#include "r8a7778.dtsi"
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/gpio/gpio.h>
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/ {
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model = "bockw";
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compatible = "renesas,bockw-reference", "renesas,r8a7778";
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chosen {
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bootargs = "console=ttySC0,115200 ignore_loglevel root=/dev/nfs ip=dhcp rw";
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};
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memory {
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device_type = "memory";
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reg = <0x60000000 0x10000000>;
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};
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fixedregulator3v3: fixedregulator@0 {
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compatible = "regulator-fixed";
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regulator-name = "fixed-3.3V";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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ethernet@18300000 {
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compatible = "smsc,lan9220", "smsc,lan9115";
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reg = <0x18300000 0x1000>;
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phy-mode = "mii";
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interrupt-parent = <&irqpin>;
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interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
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reg-io-width = <4>;
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vddvario-supply = <&fixedregulator3v3>;
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vdd33a-supply = <&fixedregulator3v3>;
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};
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};
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&mmcif {
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pinctrl-0 = <&mmc_pins>;
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pinctrl-names = "default";
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vmmc-supply = <&fixedregulator3v3>;
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bus-width = <8>;
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broken-cd;
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status = "okay";
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};
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&irqpin {
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status = "okay";
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};
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&pfc {
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pinctrl-0 = <&scif0_pins>;
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pinctrl-names = "default";
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scif0_pins: serial0 {
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renesas,groups = "scif0_data_a", "scif0_ctrl";
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renesas,function = "scif0";
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};
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mmc_pins: mmc {
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renesas,groups = "mmc_data8", "mmc_ctrl";
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renesas,function = "mmc";
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};
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sdhi0_pins: sd0 {
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renesas,groups = "sdhi0_data4", "sdhi0_ctrl",
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"sdhi0_cd";
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renesas,function = "sdhi0";
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};
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hspi0_pins: hspi0 {
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renesas,groups = "hspi0_a";
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renesas,function = "hspi0";
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};
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};
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&sdhi0 {
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pinctrl-0 = <&sdhi0_pins>;
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pinctrl-names = "default";
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vmmc-supply = <&fixedregulator3v3>;
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bus-width = <4>;
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status = "okay";
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wp-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>;
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};
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&hspi0 {
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pinctrl-0 = <&hspi0_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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