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5070158804
The "index" field of struct cpufreq_frequency_table was never an index and isn't used at all by the cpufreq core. It only is useful for cpufreq drivers for their internal purposes. Many people nowadays blindly set it in ascending order with the assumption that the core will use it, which is a mistake. Rename it to "driver_data" as that's what its purpose is. All of its users are updated accordingly. [rjw: Changelog] Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
147 lines
3.1 KiB
C
147 lines
3.1 KiB
C
/*
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* Copyright (C) 2006 - 2008 Lemote Inc. & Insititute of Computing Technology
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* Author: Yanhua, yanh@lemote.com
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/clk.h>
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#include <linux/cpufreq.h>
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#include <linux/errno.h>
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#include <linux/export.h>
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#include <linux/init.h>
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#include <linux/list.h>
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#include <linux/mutex.h>
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#include <linux/spinlock.h>
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#include <asm/clock.h>
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#include <asm/mach-loongson/loongson.h>
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static LIST_HEAD(clock_list);
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static DEFINE_SPINLOCK(clock_lock);
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static DEFINE_MUTEX(clock_list_sem);
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/* Minimum CLK support */
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enum {
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DC_ZERO, DC_25PT = 2, DC_37PT, DC_50PT, DC_62PT, DC_75PT,
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DC_87PT, DC_DISABLE, DC_RESV
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};
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struct cpufreq_frequency_table loongson2_clockmod_table[] = {
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{DC_RESV, CPUFREQ_ENTRY_INVALID},
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{DC_ZERO, CPUFREQ_ENTRY_INVALID},
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{DC_25PT, 0},
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{DC_37PT, 0},
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{DC_50PT, 0},
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{DC_62PT, 0},
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{DC_75PT, 0},
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{DC_87PT, 0},
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{DC_DISABLE, 0},
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{DC_RESV, CPUFREQ_TABLE_END},
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};
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EXPORT_SYMBOL_GPL(loongson2_clockmod_table);
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static struct clk cpu_clk = {
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.name = "cpu_clk",
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.flags = CLK_ALWAYS_ENABLED | CLK_RATE_PROPAGATES,
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.rate = 800000000,
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};
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struct clk *clk_get(struct device *dev, const char *id)
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{
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return &cpu_clk;
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}
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EXPORT_SYMBOL(clk_get);
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static void propagate_rate(struct clk *clk)
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{
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struct clk *clkp;
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list_for_each_entry(clkp, &clock_list, node) {
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if (likely(clkp->parent != clk))
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continue;
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if (likely(clkp->ops && clkp->ops->recalc))
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clkp->ops->recalc(clkp);
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if (unlikely(clkp->flags & CLK_RATE_PROPAGATES))
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propagate_rate(clkp);
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}
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}
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int clk_enable(struct clk *clk)
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{
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return 0;
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}
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EXPORT_SYMBOL(clk_enable);
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void clk_disable(struct clk *clk)
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{
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}
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EXPORT_SYMBOL(clk_disable);
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unsigned long clk_get_rate(struct clk *clk)
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{
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return (unsigned long)clk->rate;
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}
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EXPORT_SYMBOL(clk_get_rate);
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void clk_put(struct clk *clk)
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{
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}
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EXPORT_SYMBOL(clk_put);
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int clk_set_rate(struct clk *clk, unsigned long rate)
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{
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int ret = 0;
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int regval;
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int i;
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if (likely(clk->ops && clk->ops->set_rate)) {
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unsigned long flags;
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spin_lock_irqsave(&clock_lock, flags);
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ret = clk->ops->set_rate(clk, rate, 0);
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spin_unlock_irqrestore(&clock_lock, flags);
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}
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if (unlikely(clk->flags & CLK_RATE_PROPAGATES))
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propagate_rate(clk);
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for (i = 0; loongson2_clockmod_table[i].frequency != CPUFREQ_TABLE_END;
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i++) {
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if (loongson2_clockmod_table[i].frequency ==
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CPUFREQ_ENTRY_INVALID)
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continue;
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if (rate == loongson2_clockmod_table[i].frequency)
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break;
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}
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if (rate != loongson2_clockmod_table[i].frequency)
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return -ENOTSUPP;
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clk->rate = rate;
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regval = LOONGSON_CHIPCFG0;
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regval = (regval & ~0x7) |
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(loongson2_clockmod_table[i].driver_data - 1);
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LOONGSON_CHIPCFG0 = regval;
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return ret;
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}
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EXPORT_SYMBOL_GPL(clk_set_rate);
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long clk_round_rate(struct clk *clk, unsigned long rate)
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{
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if (likely(clk->ops && clk->ops->round_rate)) {
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unsigned long flags, rounded;
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spin_lock_irqsave(&clock_lock, flags);
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rounded = clk->ops->round_rate(clk, rate);
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spin_unlock_irqrestore(&clock_lock, flags);
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return rounded;
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}
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return rate;
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}
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EXPORT_SYMBOL_GPL(clk_round_rate);
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