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a439fe51a1
The majority of this patch was created by the following script: *** ASM=arch/sparc/include/asm mkdir -p $ASM git mv include/asm-sparc64/ftrace.h $ASM git rm include/asm-sparc64/* git mv include/asm-sparc/* $ASM sed -ie 's/asm-sparc64/asm/g' $ASM/* sed -ie 's/asm-sparc/asm/g' $ASM/* *** The rest was an update of the top-level Makefile to use sparc for header files when sparc64 is being build. And a small fixlet to pick up the correct unistd.h from sparc64 code. Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
94 lines
2.8 KiB
C
94 lines
2.8 KiB
C
/*
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* psr.h: This file holds the macros for masking off various parts of
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* the processor status register on the Sparc. This is valid
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* for Version 8. On the V9 this is renamed to the PSTATE
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* register and its members are accessed as fields like
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* PSTATE.PRIV for the current CPU privilege level.
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*
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* Copyright (C) 1994 David S. Miller (davem@caip.rutgers.edu)
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*/
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#ifndef __LINUX_SPARC_PSR_H
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#define __LINUX_SPARC_PSR_H
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/* The Sparc PSR fields are laid out as the following:
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*
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* ------------------------------------------------------------------------
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* | impl | vers | icc | resv | EC | EF | PIL | S | PS | ET | CWP |
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* | 31-28 | 27-24 | 23-20 | 19-14 | 13 | 12 | 11-8 | 7 | 6 | 5 | 4-0 |
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* ------------------------------------------------------------------------
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*/
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#define PSR_CWP 0x0000001f /* current window pointer */
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#define PSR_ET 0x00000020 /* enable traps field */
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#define PSR_PS 0x00000040 /* previous privilege level */
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#define PSR_S 0x00000080 /* current privilege level */
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#define PSR_PIL 0x00000f00 /* processor interrupt level */
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#define PSR_EF 0x00001000 /* enable floating point */
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#define PSR_EC 0x00002000 /* enable co-processor */
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#define PSR_SYSCALL 0x00004000 /* inside of a syscall */
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#define PSR_LE 0x00008000 /* SuperSparcII little-endian */
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#define PSR_ICC 0x00f00000 /* integer condition codes */
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#define PSR_C 0x00100000 /* carry bit */
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#define PSR_V 0x00200000 /* overflow bit */
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#define PSR_Z 0x00400000 /* zero bit */
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#define PSR_N 0x00800000 /* negative bit */
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#define PSR_VERS 0x0f000000 /* cpu-version field */
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#define PSR_IMPL 0xf0000000 /* cpu-implementation field */
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#ifdef __KERNEL__
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#ifndef __ASSEMBLY__
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/* Get the %psr register. */
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static inline unsigned int get_psr(void)
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{
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unsigned int psr;
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__asm__ __volatile__(
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"rd %%psr, %0\n\t"
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"nop\n\t"
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"nop\n\t"
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"nop\n\t"
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: "=r" (psr)
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: /* no inputs */
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: "memory");
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return psr;
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}
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static inline void put_psr(unsigned int new_psr)
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{
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__asm__ __volatile__(
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"wr %0, 0x0, %%psr\n\t"
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"nop\n\t"
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"nop\n\t"
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"nop\n\t"
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: /* no outputs */
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: "r" (new_psr)
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: "memory", "cc");
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}
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/* Get the %fsr register. Be careful, make sure the floating point
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* enable bit is set in the %psr when you execute this or you will
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* incur a trap.
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*/
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extern unsigned int fsr_storage;
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static inline unsigned int get_fsr(void)
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{
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unsigned int fsr = 0;
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__asm__ __volatile__(
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"st %%fsr, %1\n\t"
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"ld %1, %0\n\t"
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: "=r" (fsr)
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: "m" (fsr_storage));
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return fsr;
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}
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#endif /* !(__ASSEMBLY__) */
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#endif /* (__KERNEL__) */
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#endif /* !(__LINUX_SPARC_PSR_H) */
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