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d2912cb15b
Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation # extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 4122 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Enrico Weigelt <info@metux.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
85 lines
3.2 KiB
C
85 lines
3.2 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2013 Pengutronix
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* Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
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*/
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#include <linux/io.h>
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#include <linux/clk-provider.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/slab.h>
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#include <dt-bindings/clock/efm32-cmu.h>
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#define CMU_HFPERCLKEN0 0x44
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#define CMU_MAX_CLKS 37
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static struct clk_hw_onecell_data *clk_data;
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static void __init efm32gg_cmu_init(struct device_node *np)
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{
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int i;
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void __iomem *base;
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struct clk_hw **hws;
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clk_data = kzalloc(struct_size(clk_data, hws, CMU_MAX_CLKS),
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GFP_KERNEL);
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if (!clk_data)
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return;
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hws = clk_data->hws;
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for (i = 0; i < CMU_MAX_CLKS; ++i)
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hws[i] = ERR_PTR(-ENOENT);
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base = of_iomap(np, 0);
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if (!base) {
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pr_warn("Failed to map address range for efm32gg,cmu node\n");
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return;
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}
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hws[clk_HFXO] = clk_hw_register_fixed_rate(NULL, "HFXO", NULL, 0,
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48000000);
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hws[clk_HFPERCLKUSART0] = clk_hw_register_gate(NULL, "HFPERCLK.USART0",
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"HFXO", 0, base + CMU_HFPERCLKEN0, 0, 0, NULL);
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hws[clk_HFPERCLKUSART1] = clk_hw_register_gate(NULL, "HFPERCLK.USART1",
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"HFXO", 0, base + CMU_HFPERCLKEN0, 1, 0, NULL);
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hws[clk_HFPERCLKUSART2] = clk_hw_register_gate(NULL, "HFPERCLK.USART2",
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"HFXO", 0, base + CMU_HFPERCLKEN0, 2, 0, NULL);
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hws[clk_HFPERCLKUART0] = clk_hw_register_gate(NULL, "HFPERCLK.UART0",
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"HFXO", 0, base + CMU_HFPERCLKEN0, 3, 0, NULL);
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hws[clk_HFPERCLKUART1] = clk_hw_register_gate(NULL, "HFPERCLK.UART1",
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"HFXO", 0, base + CMU_HFPERCLKEN0, 4, 0, NULL);
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hws[clk_HFPERCLKTIMER0] = clk_hw_register_gate(NULL, "HFPERCLK.TIMER0",
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"HFXO", 0, base + CMU_HFPERCLKEN0, 5, 0, NULL);
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hws[clk_HFPERCLKTIMER1] = clk_hw_register_gate(NULL, "HFPERCLK.TIMER1",
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"HFXO", 0, base + CMU_HFPERCLKEN0, 6, 0, NULL);
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hws[clk_HFPERCLKTIMER2] = clk_hw_register_gate(NULL, "HFPERCLK.TIMER2",
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"HFXO", 0, base + CMU_HFPERCLKEN0, 7, 0, NULL);
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hws[clk_HFPERCLKTIMER3] = clk_hw_register_gate(NULL, "HFPERCLK.TIMER3",
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"HFXO", 0, base + CMU_HFPERCLKEN0, 8, 0, NULL);
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hws[clk_HFPERCLKACMP0] = clk_hw_register_gate(NULL, "HFPERCLK.ACMP0",
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"HFXO", 0, base + CMU_HFPERCLKEN0, 9, 0, NULL);
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hws[clk_HFPERCLKACMP1] = clk_hw_register_gate(NULL, "HFPERCLK.ACMP1",
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"HFXO", 0, base + CMU_HFPERCLKEN0, 10, 0, NULL);
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hws[clk_HFPERCLKI2C0] = clk_hw_register_gate(NULL, "HFPERCLK.I2C0",
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"HFXO", 0, base + CMU_HFPERCLKEN0, 11, 0, NULL);
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hws[clk_HFPERCLKI2C1] = clk_hw_register_gate(NULL, "HFPERCLK.I2C1",
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"HFXO", 0, base + CMU_HFPERCLKEN0, 12, 0, NULL);
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hws[clk_HFPERCLKGPIO] = clk_hw_register_gate(NULL, "HFPERCLK.GPIO",
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"HFXO", 0, base + CMU_HFPERCLKEN0, 13, 0, NULL);
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hws[clk_HFPERCLKVCMP] = clk_hw_register_gate(NULL, "HFPERCLK.VCMP",
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"HFXO", 0, base + CMU_HFPERCLKEN0, 14, 0, NULL);
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hws[clk_HFPERCLKPRS] = clk_hw_register_gate(NULL, "HFPERCLK.PRS",
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"HFXO", 0, base + CMU_HFPERCLKEN0, 15, 0, NULL);
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hws[clk_HFPERCLKADC0] = clk_hw_register_gate(NULL, "HFPERCLK.ADC0",
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"HFXO", 0, base + CMU_HFPERCLKEN0, 16, 0, NULL);
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hws[clk_HFPERCLKDAC0] = clk_hw_register_gate(NULL, "HFPERCLK.DAC0",
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"HFXO", 0, base + CMU_HFPERCLKEN0, 17, 0, NULL);
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of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
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}
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CLK_OF_DECLARE(efm32ggcmu, "efm32gg,cmu", efm32gg_cmu_init);
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