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7d3723ba8c
Define the set of CCUs and provided clocks sufficient to satisfy the needs of all the existing clock references for BCM21664. Replace the "fake" fixed-rate clocks used previously with "real" ones. Note that only the minimal set of these clocks and CCUs is defined here. More clock definitions will need to be added as required by the addition of additional drivers. Signed-off-by: Alex Elder <elder@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
291 lines
7.4 KiB
C
291 lines
7.4 KiB
C
/*
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* Copyright (C) 2014 Broadcom Corporation
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* Copyright 2014 Linaro Limited
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include "clk-kona.h"
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#include "dt-bindings/clock/bcm21664.h"
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#define BCM21664_CCU_COMMON(_name, _capname) \
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KONA_CCU_COMMON(BCM21664, _name, _capname)
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/* Root CCU */
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static struct peri_clk_data frac_1m_data = {
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.gate = HW_SW_GATE(0x214, 16, 0, 1),
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.clocks = CLOCKS("ref_crystal"),
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};
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static struct ccu_data root_ccu_data = {
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BCM21664_CCU_COMMON(root, ROOT),
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/* no policy control */
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.kona_clks = {
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[BCM21664_ROOT_CCU_FRAC_1M] =
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KONA_CLK(root, frac_1m, peri),
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[BCM21664_ROOT_CCU_CLOCK_COUNT] = LAST_KONA_CLK,
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},
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};
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/* AON CCU */
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static struct peri_clk_data hub_timer_data = {
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.gate = HW_SW_GATE(0x0414, 16, 0, 1),
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.hyst = HYST(0x0414, 8, 9),
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.clocks = CLOCKS("bbl_32k",
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"frac_1m",
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"dft_19_5m"),
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.sel = SELECTOR(0x0a10, 0, 2),
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.trig = TRIGGER(0x0a40, 4),
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};
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static struct ccu_data aon_ccu_data = {
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BCM21664_CCU_COMMON(aon, AON),
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.policy = {
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.enable = CCU_LVM_EN(0x0034, 0),
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.control = CCU_POLICY_CTL(0x000c, 0, 1, 2),
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},
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.kona_clks = {
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[BCM21664_AON_CCU_HUB_TIMER] =
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KONA_CLK(aon, hub_timer, peri),
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[BCM21664_AON_CCU_CLOCK_COUNT] = LAST_KONA_CLK,
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},
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};
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/* Master CCU */
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static struct peri_clk_data sdio1_data = {
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.gate = HW_SW_GATE(0x0358, 18, 2, 3),
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.clocks = CLOCKS("ref_crystal",
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"var_52m",
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"ref_52m",
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"var_96m",
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"ref_96m"),
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.sel = SELECTOR(0x0a28, 0, 3),
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.div = DIVIDER(0x0a28, 4, 14),
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.trig = TRIGGER(0x0afc, 9),
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};
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static struct peri_clk_data sdio2_data = {
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.gate = HW_SW_GATE(0x035c, 18, 2, 3),
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.clocks = CLOCKS("ref_crystal",
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"var_52m",
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"ref_52m",
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"var_96m",
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"ref_96m"),
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.sel = SELECTOR(0x0a2c, 0, 3),
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.div = DIVIDER(0x0a2c, 4, 14),
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.trig = TRIGGER(0x0afc, 10),
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};
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static struct peri_clk_data sdio3_data = {
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.gate = HW_SW_GATE(0x0364, 18, 2, 3),
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.clocks = CLOCKS("ref_crystal",
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"var_52m",
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"ref_52m",
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"var_96m",
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"ref_96m"),
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.sel = SELECTOR(0x0a34, 0, 3),
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.div = DIVIDER(0x0a34, 4, 14),
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.trig = TRIGGER(0x0afc, 12),
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};
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static struct peri_clk_data sdio4_data = {
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.gate = HW_SW_GATE(0x0360, 18, 2, 3),
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.clocks = CLOCKS("ref_crystal",
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"var_52m",
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"ref_52m",
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"var_96m",
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"ref_96m"),
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.sel = SELECTOR(0x0a30, 0, 3),
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.div = DIVIDER(0x0a30, 4, 14),
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.trig = TRIGGER(0x0afc, 11),
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};
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static struct peri_clk_data sdio1_sleep_data = {
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.clocks = CLOCKS("ref_32k"), /* Verify */
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.gate = HW_SW_GATE(0x0358, 18, 2, 3),
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};
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static struct peri_clk_data sdio2_sleep_data = {
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.clocks = CLOCKS("ref_32k"), /* Verify */
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.gate = HW_SW_GATE(0x035c, 18, 2, 3),
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};
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static struct peri_clk_data sdio3_sleep_data = {
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.clocks = CLOCKS("ref_32k"), /* Verify */
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.gate = HW_SW_GATE(0x0364, 18, 2, 3),
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};
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static struct peri_clk_data sdio4_sleep_data = {
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.clocks = CLOCKS("ref_32k"), /* Verify */
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.gate = HW_SW_GATE(0x0360, 18, 2, 3),
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};
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static struct ccu_data master_ccu_data = {
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BCM21664_CCU_COMMON(master, MASTER),
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.policy = {
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.enable = CCU_LVM_EN(0x0034, 0),
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.control = CCU_POLICY_CTL(0x000c, 0, 1, 2),
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},
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.kona_clks = {
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[BCM21664_MASTER_CCU_SDIO1] =
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KONA_CLK(master, sdio1, peri),
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[BCM21664_MASTER_CCU_SDIO2] =
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KONA_CLK(master, sdio2, peri),
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[BCM21664_MASTER_CCU_SDIO3] =
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KONA_CLK(master, sdio3, peri),
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[BCM21664_MASTER_CCU_SDIO4] =
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KONA_CLK(master, sdio4, peri),
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[BCM21664_MASTER_CCU_SDIO1_SLEEP] =
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KONA_CLK(master, sdio1_sleep, peri),
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[BCM21664_MASTER_CCU_SDIO2_SLEEP] =
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KONA_CLK(master, sdio2_sleep, peri),
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[BCM21664_MASTER_CCU_SDIO3_SLEEP] =
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KONA_CLK(master, sdio3_sleep, peri),
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[BCM21664_MASTER_CCU_SDIO4_SLEEP] =
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KONA_CLK(master, sdio4_sleep, peri),
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[BCM21664_MASTER_CCU_CLOCK_COUNT] = LAST_KONA_CLK,
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},
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};
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/* Slave CCU */
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static struct peri_clk_data uartb_data = {
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.gate = HW_SW_GATE(0x0400, 18, 2, 3),
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.clocks = CLOCKS("ref_crystal",
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"var_156m",
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"ref_156m"),
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.sel = SELECTOR(0x0a10, 0, 2),
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.div = FRAC_DIVIDER(0x0a10, 4, 12, 8),
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.trig = TRIGGER(0x0afc, 2),
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};
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static struct peri_clk_data uartb2_data = {
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.gate = HW_SW_GATE(0x0404, 18, 2, 3),
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.clocks = CLOCKS("ref_crystal",
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"var_156m",
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"ref_156m"),
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.sel = SELECTOR(0x0a14, 0, 2),
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.div = FRAC_DIVIDER(0x0a14, 4, 12, 8),
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.trig = TRIGGER(0x0afc, 3),
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};
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static struct peri_clk_data uartb3_data = {
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.gate = HW_SW_GATE(0x0408, 18, 2, 3),
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.clocks = CLOCKS("ref_crystal",
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"var_156m",
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"ref_156m"),
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.sel = SELECTOR(0x0a18, 0, 2),
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.div = FRAC_DIVIDER(0x0a18, 4, 12, 8),
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.trig = TRIGGER(0x0afc, 4),
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};
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static struct peri_clk_data bsc1_data = {
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.gate = HW_SW_GATE(0x0458, 18, 2, 3),
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.clocks = CLOCKS("ref_crystal",
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"var_104m",
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"ref_104m",
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"var_13m",
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"ref_13m"),
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.sel = SELECTOR(0x0a64, 0, 3),
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.trig = TRIGGER(0x0afc, 23),
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};
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static struct peri_clk_data bsc2_data = {
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.gate = HW_SW_GATE(0x045c, 18, 2, 3),
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.clocks = CLOCKS("ref_crystal",
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"var_104m",
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"ref_104m",
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"var_13m",
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"ref_13m"),
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.sel = SELECTOR(0x0a68, 0, 3),
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.trig = TRIGGER(0x0afc, 24),
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};
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static struct peri_clk_data bsc3_data = {
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.gate = HW_SW_GATE(0x0470, 18, 2, 3),
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.clocks = CLOCKS("ref_crystal",
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"var_104m",
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"ref_104m",
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"var_13m",
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"ref_13m"),
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.sel = SELECTOR(0x0a7c, 0, 3),
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.trig = TRIGGER(0x0afc, 18),
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};
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static struct peri_clk_data bsc4_data = {
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.gate = HW_SW_GATE(0x0474, 18, 2, 3),
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.clocks = CLOCKS("ref_crystal",
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"var_104m",
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"ref_104m",
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"var_13m",
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"ref_13m"),
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.sel = SELECTOR(0x0a80, 0, 3),
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.trig = TRIGGER(0x0afc, 19),
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};
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static struct ccu_data slave_ccu_data = {
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BCM21664_CCU_COMMON(slave, SLAVE),
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.policy = {
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.enable = CCU_LVM_EN(0x0034, 0),
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.control = CCU_POLICY_CTL(0x000c, 0, 1, 2),
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},
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.kona_clks = {
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[BCM21664_SLAVE_CCU_UARTB] =
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KONA_CLK(slave, uartb, peri),
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[BCM21664_SLAVE_CCU_UARTB2] =
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KONA_CLK(slave, uartb2, peri),
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[BCM21664_SLAVE_CCU_UARTB3] =
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KONA_CLK(slave, uartb3, peri),
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[BCM21664_SLAVE_CCU_BSC1] =
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KONA_CLK(slave, bsc1, peri),
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[BCM21664_SLAVE_CCU_BSC2] =
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KONA_CLK(slave, bsc2, peri),
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[BCM21664_SLAVE_CCU_BSC3] =
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KONA_CLK(slave, bsc3, peri),
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[BCM21664_SLAVE_CCU_BSC4] =
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KONA_CLK(slave, bsc4, peri),
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[BCM21664_SLAVE_CCU_CLOCK_COUNT] = LAST_KONA_CLK,
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},
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};
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/* Device tree match table callback functions */
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static void __init kona_dt_root_ccu_setup(struct device_node *node)
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{
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kona_dt_ccu_setup(&root_ccu_data, node);
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}
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static void __init kona_dt_aon_ccu_setup(struct device_node *node)
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{
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kona_dt_ccu_setup(&aon_ccu_data, node);
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}
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static void __init kona_dt_master_ccu_setup(struct device_node *node)
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{
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kona_dt_ccu_setup(&master_ccu_data, node);
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}
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static void __init kona_dt_slave_ccu_setup(struct device_node *node)
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{
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kona_dt_ccu_setup(&slave_ccu_data, node);
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}
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CLK_OF_DECLARE(bcm21664_root_ccu, BCM21664_DT_ROOT_CCU_COMPAT,
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kona_dt_root_ccu_setup);
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CLK_OF_DECLARE(bcm21664_aon_ccu, BCM21664_DT_AON_CCU_COMPAT,
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kona_dt_aon_ccu_setup);
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CLK_OF_DECLARE(bcm21664_master_ccu, BCM21664_DT_MASTER_CCU_COMPAT,
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kona_dt_master_ccu_setup);
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CLK_OF_DECLARE(bcm21664_slave_ccu, BCM21664_DT_SLAVE_CCU_COMPAT,
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kona_dt_slave_ccu_setup);
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