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https://github.com/edk2-porting/linux-next.git
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ab7c01fdc3
There are five MIPS32/64 architecture releases currently available:
from 1 to 6 except fourth one, which was intentionally skipped.
Three of them can be called as major: 1st, 2nd and 6th, that not only
have some system level alterations, but also introduced significant
core/ISA level updates. The rest of the MIPS architecture releases are
minor.
Even though they don't have as much ISA/system/core level changes
as the major ones with respect to the previous releases, they still
provide a set of updates (I'd say they were intended to be the
intermediate releases before a major one) that might be useful for the
kernel and user-level code, when activated by the kernel or compiler.
In particular the following features were introduced or ended up being
available at/after MIPS32/64 Release 5 architecture:
+ the last release of the misaligned memory access instructions,
+ virtualisation - VZ ASE - is optional component of the arch,
+ SIMD - MSA ASE - is optional component of the arch,
+ DSP ASE is optional component of the arch,
+ CP0.Status.FR=1 for CP1.FIR.F64=1 (pure 64-bit FPU general registers)
must be available if FPU is implemented,
+ CP1.FIR.Has2008 support is required so CP1.FCSR.{ABS2008,NAN2008} bits
are available.
+ UFR/UNFR aliases to access CP0.Status.FR from user-space by means of
ctc1/cfc1 instructions (enabled by CP0.Config5.UFR),
+ CP0.COnfig5.LLB=1 and eretnc instruction are implemented to without
accidentally clearing LL-bit when returning from an interrupt,
exception, or error trap,
+ XPA feature together with extended versions of CPx registers is
introduced, which needs to have mfhc0/mthc0 instructions available.
So due to these changes GNU GCC provides an extended instructions set
support for MIPS32/64 Release 5 by default like eretnc/mfhc0/mthc0. Even
though the architecture alteration isn't that big, it still worth to be
taken into account by the kernel software. Finally we can't deny that
some optimization/limitations might be found in future and implemented
on some level in kernel or compiler. In this case having even
intermediate MIPS architecture releases support would be more than
useful.
So the most of the changes provided by this commit can be split into
either compile- or runtime configs related. The compile-time related
changes are caused by adding the new CONFIG_CPU_MIPS32_R5/CONFIG_CPU_MIPSR5
configs and concern the code activating MIPSR2 or MIPSR6 already
implemented features (like eretnc/LLbit, mthc0/mfhc0). In addition
CPU_HAS_MSA can be now freely enabled for MIPS32/64 release 5 based
platforms as this is done for CPU_MIPS32_R6 CPUs. The runtime changes
concerns the features which are handled with respect to the MIPS ISA
revision detected at run-time by means of CP0.Config.{AT,AR} bits. Alas
these fields can be used to detect either r1 or r2 or r6 releases.
But since we know which CPUs in fact support the R5 arch, we can manually
set MIPS_CPU_ISA_M32R5/MIPS_CPU_ISA_M64R5 bit of c->isa_level and then
use cpu_has_mips32r5/cpu_has_mips64r5 where it's appropriate.
Since XPA/EVA provide too complex alterationss and to have them used with
MIPS32 Release 2 charged kernels (for compatibility with current platform
configs) they are left to be setup as a separate kernel configs.
Co-developed-by: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Signed-off-by: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Paul Burton <paulburton@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
423 lines
8.5 KiB
C
423 lines
8.5 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2003, 04, 07 Ralf Baechle <ralf@linux-mips.org>
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* Copyright (C) MIPS Technologies, Inc.
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* written by Ralf Baechle <ralf@linux-mips.org>
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*/
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#ifndef _ASM_HAZARDS_H
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#define _ASM_HAZARDS_H
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#include <linux/stringify.h>
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#include <asm/compiler.h>
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#define ___ssnop \
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sll $0, $0, 1
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#define ___ehb \
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sll $0, $0, 3
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/*
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* TLB hazards
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*/
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#if (defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR5) || \
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defined(CONFIG_CPU_MIPSR6)) && \
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!defined(CONFIG_CPU_CAVIUM_OCTEON) && !defined(CONFIG_CPU_LOONGSON64)
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/*
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* MIPSR2 defines ehb for hazard avoidance
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*/
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#define __mtc0_tlbw_hazard \
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___ehb
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#define __mtc0_tlbr_hazard \
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___ehb
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#define __tlbw_use_hazard \
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___ehb
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#define __tlb_read_hazard \
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___ehb
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#define __tlb_probe_hazard \
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___ehb
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#define __irq_enable_hazard \
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___ehb
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#define __irq_disable_hazard \
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___ehb
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#define __back_to_back_c0_hazard \
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___ehb
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/*
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* gcc has a tradition of misscompiling the previous construct using the
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* address of a label as argument to inline assembler. Gas otoh has the
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* annoying difference between la and dla which are only usable for 32-bit
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* rsp. 64-bit code, so can't be used without conditional compilation.
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* The alternative is switching the assembler to 64-bit code which happens
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* to work right even for 32-bit code...
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*/
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#define instruction_hazard() \
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do { \
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unsigned long tmp; \
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\
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__asm__ __volatile__( \
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" .set push \n" \
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" .set "MIPS_ISA_LEVEL" \n" \
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" dla %0, 1f \n" \
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" jr.hb %0 \n" \
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" .set pop \n" \
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"1: \n" \
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: "=r" (tmp)); \
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} while (0)
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#elif (defined(CONFIG_CPU_MIPSR1) && !defined(CONFIG_MIPS_ALCHEMY)) || \
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defined(CONFIG_CPU_BMIPS)
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/*
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* These are slightly complicated by the fact that we guarantee R1 kernels to
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* run fine on R2 processors.
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*/
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#define __mtc0_tlbw_hazard \
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___ssnop; \
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___ssnop; \
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___ehb
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#define __mtc0_tlbr_hazard \
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___ssnop; \
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___ssnop; \
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___ehb
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#define __tlbw_use_hazard \
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___ssnop; \
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___ssnop; \
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___ssnop; \
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___ehb
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#define __tlb_read_hazard \
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___ssnop; \
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___ssnop; \
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___ssnop; \
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___ehb
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#define __tlb_probe_hazard \
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___ssnop; \
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___ssnop; \
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___ssnop; \
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___ehb
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#define __irq_enable_hazard \
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___ssnop; \
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___ssnop; \
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___ssnop; \
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___ehb
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#define __irq_disable_hazard \
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___ssnop; \
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___ssnop; \
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___ssnop; \
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___ehb
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#define __back_to_back_c0_hazard \
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___ssnop; \
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___ssnop; \
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___ssnop; \
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___ehb
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/*
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* gcc has a tradition of misscompiling the previous construct using the
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* address of a label as argument to inline assembler. Gas otoh has the
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* annoying difference between la and dla which are only usable for 32-bit
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* rsp. 64-bit code, so can't be used without conditional compilation.
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* The alternative is switching the assembler to 64-bit code which happens
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* to work right even for 32-bit code...
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*/
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#define __instruction_hazard() \
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do { \
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unsigned long tmp; \
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\
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__asm__ __volatile__( \
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" .set push \n" \
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" .set mips64r2 \n" \
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" dla %0, 1f \n" \
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" jr.hb %0 \n" \
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" .set pop \n" \
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"1: \n" \
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: "=r" (tmp)); \
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} while (0)
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#define instruction_hazard() \
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do { \
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if (cpu_has_mips_r2_r6) \
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__instruction_hazard(); \
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} while (0)
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#elif defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \
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defined(CONFIG_CPU_LOONGSON2EF) || defined(CONFIG_CPU_LOONGSON64) || \
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defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_R5500) || defined(CONFIG_CPU_XLR)
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/*
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* R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
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*/
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#define __mtc0_tlbw_hazard
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#define __mtc0_tlbr_hazard
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#define __tlbw_use_hazard
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#define __tlb_read_hazard
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#define __tlb_probe_hazard
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#define __irq_enable_hazard
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#define __irq_disable_hazard
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#define __back_to_back_c0_hazard
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#define instruction_hazard() do { } while (0)
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#elif defined(CONFIG_CPU_SB1)
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/*
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* Mostly like R4000 for historic reasons
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*/
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#define __mtc0_tlbw_hazard
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#define __mtc0_tlbr_hazard
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#define __tlbw_use_hazard
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#define __tlb_read_hazard
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#define __tlb_probe_hazard
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#define __irq_enable_hazard
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#define __irq_disable_hazard \
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___ssnop; \
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___ssnop; \
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___ssnop
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#define __back_to_back_c0_hazard
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#define instruction_hazard() do { } while (0)
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#else
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/*
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* Finally the catchall case for all other processors including R4000, R4400,
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* R4600, R4700, R5000, RM7000, NEC VR41xx etc.
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*
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* The taken branch will result in a two cycle penalty for the two killed
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* instructions on R4000 / R4400. Other processors only have a single cycle
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* hazard so this is nice trick to have an optimal code for a range of
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* processors.
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*/
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#define __mtc0_tlbw_hazard \
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nop; \
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nop
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#define __mtc0_tlbr_hazard \
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nop; \
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nop
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#define __tlbw_use_hazard \
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nop; \
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nop; \
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nop
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#define __tlb_read_hazard \
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nop; \
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nop; \
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nop
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#define __tlb_probe_hazard \
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nop; \
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nop; \
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nop
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#define __irq_enable_hazard \
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___ssnop; \
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___ssnop; \
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___ssnop
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#define __irq_disable_hazard \
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nop; \
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nop; \
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nop
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#define __back_to_back_c0_hazard \
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___ssnop; \
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___ssnop; \
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___ssnop
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#define instruction_hazard() do { } while (0)
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#endif
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/* FPU hazards */
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#if defined(CONFIG_CPU_SB1)
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#define __enable_fpu_hazard \
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.set push; \
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.set mips64; \
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.set noreorder; \
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___ssnop; \
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bnezl $0, .+4; \
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___ssnop; \
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.set pop
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#define __disable_fpu_hazard
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#elif defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR5) || \
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defined(CONFIG_CPU_MIPSR6)
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#define __enable_fpu_hazard \
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___ehb
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#define __disable_fpu_hazard \
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___ehb
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#else
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#define __enable_fpu_hazard \
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nop; \
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nop; \
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nop; \
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nop
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#define __disable_fpu_hazard \
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___ehb
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#endif
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#ifdef __ASSEMBLY__
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#define _ssnop ___ssnop
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#define _ehb ___ehb
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#define mtc0_tlbw_hazard __mtc0_tlbw_hazard
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#define mtc0_tlbr_hazard __mtc0_tlbr_hazard
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#define tlbw_use_hazard __tlbw_use_hazard
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#define tlb_read_hazard __tlb_read_hazard
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#define tlb_probe_hazard __tlb_probe_hazard
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#define irq_enable_hazard __irq_enable_hazard
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#define irq_disable_hazard __irq_disable_hazard
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#define back_to_back_c0_hazard __back_to_back_c0_hazard
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#define enable_fpu_hazard __enable_fpu_hazard
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#define disable_fpu_hazard __disable_fpu_hazard
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#else
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#define _ssnop() \
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do { \
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__asm__ __volatile__( \
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__stringify(___ssnop) \
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); \
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} while (0)
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#define _ehb() \
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do { \
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__asm__ __volatile__( \
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__stringify(___ehb) \
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); \
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} while (0)
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#define mtc0_tlbw_hazard() \
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do { \
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__asm__ __volatile__( \
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__stringify(__mtc0_tlbw_hazard) \
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); \
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} while (0)
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#define mtc0_tlbr_hazard() \
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do { \
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__asm__ __volatile__( \
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__stringify(__mtc0_tlbr_hazard) \
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); \
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} while (0)
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#define tlbw_use_hazard() \
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do { \
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__asm__ __volatile__( \
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__stringify(__tlbw_use_hazard) \
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); \
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} while (0)
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#define tlb_read_hazard() \
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do { \
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__asm__ __volatile__( \
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__stringify(__tlb_read_hazard) \
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); \
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} while (0)
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#define tlb_probe_hazard() \
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do { \
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__asm__ __volatile__( \
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__stringify(__tlb_probe_hazard) \
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); \
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} while (0)
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#define irq_enable_hazard() \
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do { \
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__asm__ __volatile__( \
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__stringify(__irq_enable_hazard) \
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); \
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} while (0)
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#define irq_disable_hazard() \
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do { \
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__asm__ __volatile__( \
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__stringify(__irq_disable_hazard) \
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); \
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} while (0)
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#define back_to_back_c0_hazard() \
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do { \
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__asm__ __volatile__( \
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__stringify(__back_to_back_c0_hazard) \
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); \
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} while (0)
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#define enable_fpu_hazard() \
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do { \
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__asm__ __volatile__( \
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__stringify(__enable_fpu_hazard) \
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); \
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} while (0)
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#define disable_fpu_hazard() \
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do { \
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__asm__ __volatile__( \
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__stringify(__disable_fpu_hazard) \
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); \
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} while (0)
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/*
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* MIPS R2 instruction hazard barrier. Needs to be called as a subroutine.
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*/
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extern void mips_ihb(void);
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#endif /* __ASSEMBLY__ */
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#endif /* _ASM_HAZARDS_H */
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