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aac3d0c875
Untested. As this typo was introduced in v3.3, with commit
9d67028090
("powerpc: Split ICSWX ACOP and
PID processing"), which actually added PPC_ICSWX_PID, this surely needs
testing.
Signed-off-by: Paul Bolle <pebolle@tiscali.nl>
Signed-off-by: Michael Ellerman <michael@ellerman.id.au>
293 lines
7.9 KiB
C
293 lines
7.9 KiB
C
/*
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* ICSWX and ACOP Management
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*
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* Copyright (C) 2011 Anton Blanchard, IBM Corp. <anton@samba.org>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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*/
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#include <linux/sched.h>
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/types.h>
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#include <linux/mm.h>
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#include <linux/spinlock.h>
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#include <linux/module.h>
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#include <linux/uaccess.h>
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#include "icswx.h"
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/*
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* The processor and its L2 cache cause the icswx instruction to
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* generate a COP_REQ transaction on PowerBus. The transaction has no
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* address, and the processor does not perform an MMU access to
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* authenticate the transaction. The command portion of the PowerBus
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* COP_REQ transaction includes the LPAR_ID (LPID) and the coprocessor
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* Process ID (PID), which the coprocessor compares to the authorized
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* LPID and PID held in the coprocessor, to determine if the process
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* is authorized to generate the transaction. The data of the COP_REQ
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* transaction is 128-byte or less in size and is placed in cacheable
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* memory on a 128-byte cache line boundary.
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*
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* The task to use a coprocessor should use use_cop() to mark the use
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* of the Coprocessor Type (CT) and context switching. On a server
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* class processor, the PID register is used only for coprocessor
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* management + * and so a coprocessor PID is allocated before
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* executing icswx + * instruction. Drop_cop() is used to free the
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* coprocessor PID.
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*
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* Example:
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* Host Fabric Interface (HFI) is a PowerPC network coprocessor.
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* Each HFI have multiple windows. Each HFI window serves as a
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* network device sending to and receiving from HFI network.
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* HFI immediate send function uses icswx instruction. The immediate
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* send function allows small (single cache-line) packets be sent
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* without using the regular HFI send FIFO and doorbell, which are
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* much slower than immediate send.
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*
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* For each task intending to use HFI immediate send, the HFI driver
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* calls use_cop() to obtain a coprocessor PID for the task.
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* The HFI driver then allocate a free HFI window and save the
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* coprocessor PID to the HFI window to allow the task to use the
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* HFI window.
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*
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* The HFI driver repeatedly creates immediate send packets and
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* issues icswx instruction to send data through the HFI window.
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* The HFI compares the coprocessor PID in the CPU PID register
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* to the PID held in the HFI window to determine if the transaction
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* is allowed.
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*
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* When the task to release the HFI window, the HFI driver calls
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* drop_cop() to release the coprocessor PID.
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*/
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void switch_cop(struct mm_struct *next)
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{
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#ifdef CONFIG_PPC_ICSWX_PID
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mtspr(SPRN_PID, next->context.cop_pid);
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#endif
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mtspr(SPRN_ACOP, next->context.acop);
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}
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/**
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* Start using a coprocessor.
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* @acop: mask of coprocessor to be used.
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* @mm: The mm the coprocessor to associate with. Most likely current mm.
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*
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* Return a positive PID if successful. Negative errno otherwise.
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* The returned PID will be fed to the coprocessor to determine if an
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* icswx transaction is authenticated.
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*/
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int use_cop(unsigned long acop, struct mm_struct *mm)
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{
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int ret;
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if (!cpu_has_feature(CPU_FTR_ICSWX))
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return -ENODEV;
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if (!mm || !acop)
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return -EINVAL;
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/* The page_table_lock ensures mm_users won't change under us */
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spin_lock(&mm->page_table_lock);
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spin_lock(mm->context.cop_lockp);
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ret = get_cop_pid(mm);
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if (ret < 0)
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goto out;
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/* update acop */
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mm->context.acop |= acop;
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sync_cop(mm);
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/*
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* If this is a threaded process then there might be other threads
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* running. We need to send an IPI to force them to pick up any
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* change in PID and ACOP.
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*/
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if (atomic_read(&mm->mm_users) > 1)
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smp_call_function(sync_cop, mm, 1);
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out:
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spin_unlock(mm->context.cop_lockp);
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spin_unlock(&mm->page_table_lock);
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return ret;
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}
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EXPORT_SYMBOL_GPL(use_cop);
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/**
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* Stop using a coprocessor.
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* @acop: mask of coprocessor to be stopped.
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* @mm: The mm the coprocessor associated with.
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*/
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void drop_cop(unsigned long acop, struct mm_struct *mm)
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{
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int free_pid;
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if (!cpu_has_feature(CPU_FTR_ICSWX))
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return;
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if (WARN_ON_ONCE(!mm))
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return;
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/* The page_table_lock ensures mm_users won't change under us */
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spin_lock(&mm->page_table_lock);
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spin_lock(mm->context.cop_lockp);
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mm->context.acop &= ~acop;
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free_pid = disable_cop_pid(mm);
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sync_cop(mm);
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/*
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* If this is a threaded process then there might be other threads
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* running. We need to send an IPI to force them to pick up any
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* change in PID and ACOP.
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*/
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if (atomic_read(&mm->mm_users) > 1)
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smp_call_function(sync_cop, mm, 1);
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if (free_pid != COP_PID_NONE)
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free_cop_pid(free_pid);
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spin_unlock(mm->context.cop_lockp);
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spin_unlock(&mm->page_table_lock);
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}
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EXPORT_SYMBOL_GPL(drop_cop);
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static int acop_use_cop(int ct)
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{
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/* There is no alternate policy, yet */
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return -1;
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}
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/*
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* Get the instruction word at the NIP
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*/
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static u32 acop_get_inst(struct pt_regs *regs)
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{
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u32 inst;
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u32 __user *p;
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p = (u32 __user *)regs->nip;
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if (!access_ok(VERIFY_READ, p, sizeof(*p)))
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return 0;
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if (__get_user(inst, p))
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return 0;
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return inst;
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}
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/**
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* @regs: regsiters at time of interrupt
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* @address: storage address
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* @error_code: Fault code, usually the DSISR or ESR depending on
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* processor type
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*
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* Return 0 if we are able to resolve the data storage fault that
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* results from a CT miss in the ACOP register.
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*/
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int acop_handle_fault(struct pt_regs *regs, unsigned long address,
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unsigned long error_code)
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{
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int ct;
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u32 inst = 0;
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if (!cpu_has_feature(CPU_FTR_ICSWX)) {
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pr_info("No coprocessors available");
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_exception(SIGILL, regs, ILL_ILLOPN, address);
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}
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if (!user_mode(regs)) {
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/* this could happen if the HV denies the
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* kernel access, for now we just die */
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die("ICSWX from kernel failed", regs, SIGSEGV);
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}
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/* Some implementations leave us a hint for the CT */
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ct = ICSWX_GET_CT_HINT(error_code);
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if (ct < 0) {
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/* we have to peek at the instruction word to figure out CT */
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u32 ccw;
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u32 rs;
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inst = acop_get_inst(regs);
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if (inst == 0)
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return -1;
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rs = (inst >> (31 - 10)) & 0x1f;
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ccw = regs->gpr[rs];
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ct = (ccw >> 16) & 0x3f;
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}
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/*
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* We could be here because another thread has enabled acop
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* but the ACOP register has yet to be updated.
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*
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* This should have been taken care of by the IPI to sync all
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* the threads (see smp_call_function(sync_cop, mm, 1)), but
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* that could take forever if there are a significant amount
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* of threads.
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*
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* Given the number of threads on some of these systems,
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* perhaps this is the best way to sync ACOP rather than whack
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* every thread with an IPI.
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*/
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if ((acop_copro_type_bit(ct) & current->active_mm->context.acop) != 0) {
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sync_cop(current->active_mm);
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return 0;
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}
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/* check for alternate policy */
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if (!acop_use_cop(ct))
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return 0;
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/* at this point the CT is unknown to the system */
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pr_warn("%s[%d]: Coprocessor %d is unavailable\n",
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current->comm, current->pid, ct);
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/* get inst if we don't already have it */
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if (inst == 0) {
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inst = acop_get_inst(regs);
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if (inst == 0)
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return -1;
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}
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/* Check if the instruction is the "record form" */
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if (inst & 1) {
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/*
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* the instruction is "record" form so we can reject
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* using CR0
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*/
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regs->ccr &= ~(0xful << 28);
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regs->ccr |= ICSWX_RC_NOT_FOUND << 28;
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/* Move on to the next instruction */
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regs->nip += 4;
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} else {
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/*
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* There is no architected mechanism to report a bad
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* CT so we could either SIGILL or report nothing.
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* Since the non-record version should only bu used
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* for "hints" or "don't care" we should probably do
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* nothing. However, I could see how some people
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* might want an SIGILL so it here if you want it.
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*/
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#ifdef CONFIG_PPC_ICSWX_USE_SIGILL
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_exception(SIGILL, regs, ILL_ILLOPN, address);
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#else
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regs->nip += 4;
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#endif
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}
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return 0;
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}
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EXPORT_SYMBOL_GPL(acop_handle_fault);
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