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7abec10c62
* 'next/cleanup3' of git://git.linaro.org/people/arnd/arm-soc: (79 commits)
ARM: SAMSUNG: Move fimc plat. device from board files to plat-samsung
ARM: SAMSUNG: Cleanup resources by using macro
ARM: SAMSUNG: Cleanup plat-samsung/devs.c and devs.h
ARM: S5P: To merge devs.c files to one devs.c
ARM: S3C64XX: To merge devs.c files to one devs.c
ARM: S3C24XX: To merge s3c24xx devs.c files to one devs.c
ARM: S5P64X0: Add Power Management support
ARM: S5P: Make the sleep code common for S5P series SoCs
ARM: S5P: Make the common S5P PM code conditionally compile
ARM: SAMSUNG: Move S5P header files to plat-samsung
ARM: SAMSUNG: Move S3C24XX header files to plat-samsung
ARM: SAMSUNG: Moving each SoC support header files
ARM: SAMSUNG: Consolidate plat/pll.h
ARM: SAMSUNG: Consolidate plat/pwm-clock.h
ARM: SAMSUNG: Cleanup mach/clkdev.h
ARM: SAMSUNG: remove sdhci default configuration setup platform helper
ARM: EXYNOS4: Add FIMC device on SMDKV310 board
ARM: EXYNOS4: Add header file protection macros
ARM: EXYNOS4: Add usb ehci device to the SMDKV310
ARM: S3C2443: Add hsspi-clock from pclk and rename S3C2443 hsspi sclk
...
Fix up conflicts in
- arch/arm/mach-exynos4/{Kconfig,clock.c}
ARM_CPU_SUSPEND, various random device tables (gah!)
- drivers/gpio/Makefile
sa1100 gpio added, samsung gpio drivers merged
81 lines
2.5 KiB
C
81 lines
2.5 KiB
C
/* linux/arch/arm/plat-samsung/include/plat/irqs.h
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*
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* Copyright (c) 2009 Samsung Electronics Co., Ltd.
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* http://www.samsung.com/
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*
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* S5P Common IRQ support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __PLAT_SAMSUNG_IRQS_H
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#define __PLAT_SAMSUNG_IRQS_H __FILE__
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/* we keep the first set of CPU IRQs out of the range of
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* the ISA space, so that the PC104 has them to itself
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* and we don't end up having to do horrible things to the
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* standard ISA drivers....
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*
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* note, since we're using the VICs, our start must be a
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* mulitple of 32 to allow the common code to work
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*/
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#define S5P_IRQ_OFFSET (32)
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#define S5P_IRQ(x) ((x) + S5P_IRQ_OFFSET)
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#define S5P_VIC0_BASE S5P_IRQ(0)
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#define S5P_VIC1_BASE S5P_IRQ(32)
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#define S5P_VIC2_BASE S5P_IRQ(64)
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#define S5P_VIC3_BASE S5P_IRQ(96)
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#define VIC_BASE(x) (S5P_VIC0_BASE + ((x)*32))
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#define IRQ_VIC0_BASE S5P_VIC0_BASE
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#define IRQ_VIC1_BASE S5P_VIC1_BASE
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#define IRQ_VIC2_BASE S5P_VIC2_BASE
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/* VIC based IRQs */
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#define S5P_IRQ_VIC0(x) (S5P_VIC0_BASE + (x))
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#define S5P_IRQ_VIC1(x) (S5P_VIC1_BASE + (x))
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#define S5P_IRQ_VIC2(x) (S5P_VIC2_BASE + (x))
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#define S5P_IRQ_VIC3(x) (S5P_VIC3_BASE + (x))
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#define S5P_TIMER_IRQ(x) (11 + (x))
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#define IRQ_TIMER0 S5P_TIMER_IRQ(0)
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#define IRQ_TIMER1 S5P_TIMER_IRQ(1)
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#define IRQ_TIMER2 S5P_TIMER_IRQ(2)
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#define IRQ_TIMER3 S5P_TIMER_IRQ(3)
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#define IRQ_TIMER4 S5P_TIMER_IRQ(4)
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#define IRQ_EINT(x) ((x) < 16 ? ((x) + S5P_EINT_BASE1) \
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: ((x) - 16 + S5P_EINT_BASE2))
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#define EINT_OFFSET(irq) ((irq) < S5P_EINT_BASE2 ? \
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((irq) - S5P_EINT_BASE1) : \
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((irq) + 16 - S5P_EINT_BASE2))
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#define IRQ_EINT_BIT(x) EINT_OFFSET(x)
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/* Typically only a few gpio chips require gpio interrupt support.
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To avoid memory waste irq descriptors are allocated only for
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S5P_GPIOINT_GROUP_COUNT chips, each with total number of
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S5P_GPIOINT_GROUP_SIZE pins/irqs. Each GPIOINT group can be assiged
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to any gpio chip with the s5p_register_gpio_interrupt() function */
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#define S5P_GPIOINT_GROUP_COUNT 4
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#define S5P_GPIOINT_GROUP_SIZE 8
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#define S5P_GPIOINT_COUNT (S5P_GPIOINT_GROUP_COUNT * S5P_GPIOINT_GROUP_SIZE)
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/* IRQ types common for all s5p platforms */
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#define S5P_IRQ_TYPE_LEVEL_LOW (0x00)
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#define S5P_IRQ_TYPE_LEVEL_HIGH (0x01)
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#define S5P_IRQ_TYPE_EDGE_FALLING (0x02)
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#define S5P_IRQ_TYPE_EDGE_RISING (0x03)
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#define S5P_IRQ_TYPE_EDGE_BOTH (0x04)
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#endif /* __PLAT_SAMSUNG_IRQS_H */
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