mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-29 15:43:59 +08:00
426 lines
11 KiB
C
426 lines
11 KiB
C
/*
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* Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
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* Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/i2c.h>
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#include <linux/gpio.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/input.h>
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#include <linux/spi/flash.h>
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#include <linux/spi/spi.h>
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#include <mach/common.h>
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#include <mach/hardware.h>
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#include <mach/iomux-mx51.h>
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#include <asm/irq.h>
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#include <asm/setup.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/time.h>
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#include "devices-imx51.h"
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#include "devices.h"
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#include "cpu_op-mx51.h"
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#define BABBAGE_USB_HUB_RESET IMX_GPIO_NR(1, 7)
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#define BABBAGE_USBH1_STP IMX_GPIO_NR(1, 27)
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#define BABBAGE_USB_PHY_RESET IMX_GPIO_NR(2, 5)
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#define BABBAGE_FEC_PHY_RESET IMX_GPIO_NR(2, 14)
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#define BABBAGE_POWER_KEY IMX_GPIO_NR(2, 21)
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#define BABBAGE_ECSPI1_CS0 IMX_GPIO_NR(4, 24)
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#define BABBAGE_ECSPI1_CS1 IMX_GPIO_NR(4, 25)
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#define BABBAGE_SD2_CD IMX_GPIO_NR(1, 6)
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#define BABBAGE_SD2_WP IMX_GPIO_NR(1, 5)
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/* USB_CTRL_1 */
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#define MX51_USB_CTRL_1_OFFSET 0x10
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#define MX51_USB_CTRL_UH1_EXT_CLK_EN (1 << 25)
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#define MX51_USB_PLLDIV_12_MHZ 0x00
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#define MX51_USB_PLL_DIV_19_2_MHZ 0x01
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#define MX51_USB_PLL_DIV_24_MHZ 0x02
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static struct gpio_keys_button babbage_buttons[] = {
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{
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.gpio = BABBAGE_POWER_KEY,
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.code = BTN_0,
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.desc = "PWR",
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.active_low = 1,
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.wakeup = 1,
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},
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};
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static const struct gpio_keys_platform_data imx_button_data __initconst = {
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.buttons = babbage_buttons,
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.nbuttons = ARRAY_SIZE(babbage_buttons),
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};
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static iomux_v3_cfg_t mx51babbage_pads[] = {
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/* UART1 */
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MX51_PAD_UART1_RXD__UART1_RXD,
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MX51_PAD_UART1_TXD__UART1_TXD,
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MX51_PAD_UART1_RTS__UART1_RTS,
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MX51_PAD_UART1_CTS__UART1_CTS,
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/* UART2 */
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MX51_PAD_UART2_RXD__UART2_RXD,
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MX51_PAD_UART2_TXD__UART2_TXD,
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/* UART3 */
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MX51_PAD_EIM_D25__UART3_RXD,
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MX51_PAD_EIM_D26__UART3_TXD,
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MX51_PAD_EIM_D27__UART3_RTS,
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MX51_PAD_EIM_D24__UART3_CTS,
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/* I2C1 */
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MX51_PAD_EIM_D16__I2C1_SDA,
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MX51_PAD_EIM_D19__I2C1_SCL,
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/* I2C2 */
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MX51_PAD_KEY_COL4__I2C2_SCL,
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MX51_PAD_KEY_COL5__I2C2_SDA,
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/* HSI2C */
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MX51_PAD_I2C1_CLK__I2C1_CLK,
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MX51_PAD_I2C1_DAT__I2C1_DAT,
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/* USB HOST1 */
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MX51_PAD_USBH1_CLK__USBH1_CLK,
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MX51_PAD_USBH1_DIR__USBH1_DIR,
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MX51_PAD_USBH1_NXT__USBH1_NXT,
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MX51_PAD_USBH1_DATA0__USBH1_DATA0,
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MX51_PAD_USBH1_DATA1__USBH1_DATA1,
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MX51_PAD_USBH1_DATA2__USBH1_DATA2,
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MX51_PAD_USBH1_DATA3__USBH1_DATA3,
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MX51_PAD_USBH1_DATA4__USBH1_DATA4,
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MX51_PAD_USBH1_DATA5__USBH1_DATA5,
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MX51_PAD_USBH1_DATA6__USBH1_DATA6,
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MX51_PAD_USBH1_DATA7__USBH1_DATA7,
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/* USB HUB reset line*/
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MX51_PAD_GPIO1_7__GPIO1_7,
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/* USB PHY reset line */
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MX51_PAD_EIM_D21__GPIO2_5,
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/* FEC */
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MX51_PAD_EIM_EB2__FEC_MDIO,
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MX51_PAD_EIM_EB3__FEC_RDATA1,
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MX51_PAD_EIM_CS2__FEC_RDATA2,
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MX51_PAD_EIM_CS3__FEC_RDATA3,
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MX51_PAD_EIM_CS4__FEC_RX_ER,
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MX51_PAD_EIM_CS5__FEC_CRS,
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MX51_PAD_NANDF_RB2__FEC_COL,
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MX51_PAD_NANDF_RB3__FEC_RX_CLK,
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MX51_PAD_NANDF_D9__FEC_RDATA0,
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MX51_PAD_NANDF_D8__FEC_TDATA0,
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MX51_PAD_NANDF_CS2__FEC_TX_ER,
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MX51_PAD_NANDF_CS3__FEC_MDC,
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MX51_PAD_NANDF_CS4__FEC_TDATA1,
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MX51_PAD_NANDF_CS5__FEC_TDATA2,
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MX51_PAD_NANDF_CS6__FEC_TDATA3,
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MX51_PAD_NANDF_CS7__FEC_TX_EN,
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MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK,
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/* FEC PHY reset line */
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MX51_PAD_EIM_A20__GPIO2_14,
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/* SD 1 */
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MX51_PAD_SD1_CMD__SD1_CMD,
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MX51_PAD_SD1_CLK__SD1_CLK,
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MX51_PAD_SD1_DATA0__SD1_DATA0,
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MX51_PAD_SD1_DATA1__SD1_DATA1,
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MX51_PAD_SD1_DATA2__SD1_DATA2,
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MX51_PAD_SD1_DATA3__SD1_DATA3,
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/* CD/WP from controller */
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MX51_PAD_GPIO1_0__SD1_CD,
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MX51_PAD_GPIO1_1__SD1_WP,
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/* SD 2 */
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MX51_PAD_SD2_CMD__SD2_CMD,
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MX51_PAD_SD2_CLK__SD2_CLK,
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MX51_PAD_SD2_DATA0__SD2_DATA0,
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MX51_PAD_SD2_DATA1__SD2_DATA1,
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MX51_PAD_SD2_DATA2__SD2_DATA2,
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MX51_PAD_SD2_DATA3__SD2_DATA3,
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/* CD/WP gpio */
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MX51_PAD_GPIO1_6__GPIO1_6,
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MX51_PAD_GPIO1_5__GPIO1_5,
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/* eCSPI1 */
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MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
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MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
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MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
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MX51_PAD_CSPI1_SS0__GPIO4_24,
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MX51_PAD_CSPI1_SS1__GPIO4_25,
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};
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/* Serial ports */
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static const struct imxuart_platform_data uart_pdata __initconst = {
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.flags = IMXUART_HAVE_RTSCTS,
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};
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static const struct imxi2c_platform_data babbage_i2c_data __initconst = {
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.bitrate = 100000,
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};
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static struct imxi2c_platform_data babbage_hsi2c_data = {
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.bitrate = 400000,
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};
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static struct gpio mx51_babbage_usbh1_gpios[] = {
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{ BABBAGE_USBH1_STP, GPIOF_OUT_INIT_LOW, "usbh1_stp" },
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{ BABBAGE_USB_PHY_RESET, GPIOF_OUT_INIT_LOW, "usbh1_phy_reset" },
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};
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static int gpio_usbh1_active(void)
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{
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iomux_v3_cfg_t usbh1stp_gpio = MX51_PAD_USBH1_STP__GPIO1_27;
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int ret;
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/* Set USBH1_STP to GPIO and toggle it */
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mxc_iomux_v3_setup_pad(usbh1stp_gpio);
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ret = gpio_request_array(mx51_babbage_usbh1_gpios,
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ARRAY_SIZE(mx51_babbage_usbh1_gpios));
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if (ret) {
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pr_debug("failed to get USBH1 pins: %d\n", ret);
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return ret;
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}
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msleep(100);
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gpio_set_value(BABBAGE_USBH1_STP, 1);
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gpio_set_value(BABBAGE_USB_PHY_RESET, 1);
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gpio_free_array(mx51_babbage_usbh1_gpios,
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ARRAY_SIZE(mx51_babbage_usbh1_gpios));
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return 0;
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}
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static inline void babbage_usbhub_reset(void)
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{
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int ret;
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/* Reset USB hub */
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ret = gpio_request_one(BABBAGE_USB_HUB_RESET,
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GPIOF_OUT_INIT_LOW, "GPIO1_7");
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if (ret) {
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printk(KERN_ERR"failed to get GPIO_USB_HUB_RESET: %d\n", ret);
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return;
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}
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msleep(2);
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/* Deassert reset */
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gpio_set_value(BABBAGE_USB_HUB_RESET, 1);
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}
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static inline void babbage_fec_reset(void)
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{
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int ret;
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/* reset FEC PHY */
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ret = gpio_request_one(BABBAGE_FEC_PHY_RESET,
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GPIOF_OUT_INIT_LOW, "fec-phy-reset");
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if (ret) {
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printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret);
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return;
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}
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msleep(1);
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gpio_set_value(BABBAGE_FEC_PHY_RESET, 1);
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}
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/* This function is board specific as the bit mask for the plldiv will also
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be different for other Freescale SoCs, thus a common bitmask is not
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possible and cannot get place in /plat-mxc/ehci.c.*/
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static int initialize_otg_port(struct platform_device *pdev)
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{
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u32 v;
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void __iomem *usb_base;
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void __iomem *usbother_base;
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usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
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if (!usb_base)
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return -ENOMEM;
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usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
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/* Set the PHY clock to 19.2MHz */
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v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
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v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
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v |= MX51_USB_PLL_DIV_19_2_MHZ;
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__raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
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iounmap(usb_base);
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mdelay(10);
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return mx51_initialize_usb_hw(0, MXC_EHCI_INTERNAL_PHY);
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}
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static int initialize_usbh1_port(struct platform_device *pdev)
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{
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u32 v;
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void __iomem *usb_base;
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void __iomem *usbother_base;
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usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
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if (!usb_base)
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return -ENOMEM;
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usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
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/* The clock for the USBH1 ULPI port will come externally from the PHY. */
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v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET);
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__raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN, usbother_base + MX51_USB_CTRL_1_OFFSET);
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iounmap(usb_base);
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mdelay(10);
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return mx51_initialize_usb_hw(1, MXC_EHCI_POWER_PINS_ENABLED |
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MXC_EHCI_ITC_NO_THRESHOLD);
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}
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static struct mxc_usbh_platform_data dr_utmi_config = {
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.init = initialize_otg_port,
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.portsc = MXC_EHCI_UTMI_16BIT,
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};
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static struct fsl_usb2_platform_data usb_pdata = {
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.operating_mode = FSL_USB2_DR_DEVICE,
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.phy_mode = FSL_USB2_PHY_UTMI_WIDE,
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};
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static struct mxc_usbh_platform_data usbh1_config = {
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.init = initialize_usbh1_port,
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.portsc = MXC_EHCI_MODE_ULPI,
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};
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static int otg_mode_host;
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static int __init babbage_otg_mode(char *options)
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{
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if (!strcmp(options, "host"))
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otg_mode_host = 1;
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else if (!strcmp(options, "device"))
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otg_mode_host = 0;
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else
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pr_info("otg_mode neither \"host\" nor \"device\". "
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"Defaulting to device\n");
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return 0;
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}
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__setup("otg_mode=", babbage_otg_mode);
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static struct spi_board_info mx51_babbage_spi_board_info[] __initdata = {
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{
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.modalias = "mtd_dataflash",
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.max_speed_hz = 25000000,
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.bus_num = 0,
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.chip_select = 1,
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.mode = SPI_MODE_0,
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.platform_data = NULL,
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},
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};
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static int mx51_babbage_spi_cs[] = {
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BABBAGE_ECSPI1_CS0,
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BABBAGE_ECSPI1_CS1,
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};
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static const struct spi_imx_master mx51_babbage_spi_pdata __initconst = {
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.chipselect = mx51_babbage_spi_cs,
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.num_chipselect = ARRAY_SIZE(mx51_babbage_spi_cs),
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};
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static const struct esdhc_platform_data mx51_babbage_sd1_data __initconst = {
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.cd_type = ESDHC_CD_CONTROLLER,
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.wp_type = ESDHC_WP_CONTROLLER,
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};
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static const struct esdhc_platform_data mx51_babbage_sd2_data __initconst = {
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.cd_gpio = BABBAGE_SD2_CD,
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.wp_gpio = BABBAGE_SD2_WP,
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.cd_type = ESDHC_CD_GPIO,
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.wp_type = ESDHC_WP_GPIO,
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};
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/*
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* Board specific initialization.
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*/
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static void __init mx51_babbage_init(void)
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{
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iomux_v3_cfg_t usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP;
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iomux_v3_cfg_t power_key = _MX51_PAD_EIM_A27__GPIO2_21 |
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MUX_PAD_CTRL(PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP);
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imx51_soc_init();
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#if defined(CONFIG_CPU_FREQ_IMX)
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get_cpu_op = mx51_get_cpu_op;
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#endif
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mxc_iomux_v3_setup_multiple_pads(mx51babbage_pads,
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ARRAY_SIZE(mx51babbage_pads));
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imx51_add_imx_uart(0, &uart_pdata);
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imx51_add_imx_uart(1, NULL);
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imx51_add_imx_uart(2, &uart_pdata);
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babbage_fec_reset();
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imx51_add_fec(NULL);
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/* Set the PAD settings for the pwr key. */
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mxc_iomux_v3_setup_pad(power_key);
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imx_add_gpio_keys(&imx_button_data);
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imx51_add_imx_i2c(0, &babbage_i2c_data);
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imx51_add_imx_i2c(1, &babbage_i2c_data);
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mxc_register_device(&mxc_hsi2c_device, &babbage_hsi2c_data);
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if (otg_mode_host)
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mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config);
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else {
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initialize_otg_port(NULL);
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mxc_register_device(&mxc_usbdr_udc_device, &usb_pdata);
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}
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gpio_usbh1_active();
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mxc_register_device(&mxc_usbh1_device, &usbh1_config);
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/* setback USBH1_STP to be function */
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mxc_iomux_v3_setup_pad(usbh1stp);
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babbage_usbhub_reset();
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imx51_add_sdhci_esdhc_imx(0, &mx51_babbage_sd1_data);
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imx51_add_sdhci_esdhc_imx(1, &mx51_babbage_sd2_data);
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spi_register_board_info(mx51_babbage_spi_board_info,
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ARRAY_SIZE(mx51_babbage_spi_board_info));
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imx51_add_ecspi(0, &mx51_babbage_spi_pdata);
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imx51_add_imx2_wdt(0, NULL);
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}
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static void __init mx51_babbage_timer_init(void)
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{
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mx51_clocks_init(32768, 24000000, 22579200, 0);
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}
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static struct sys_timer mx51_babbage_timer = {
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.init = mx51_babbage_timer_init,
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};
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MACHINE_START(MX51_BABBAGE, "Freescale MX51 Babbage Board")
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/* Maintainer: Amit Kucheria <amit.kucheria@canonical.com> */
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.boot_params = MX51_PHYS_OFFSET + 0x100,
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.map_io = mx51_map_io,
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.init_early = imx51_init_early,
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.init_irq = mx51_init_irq,
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.timer = &mx51_babbage_timer,
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.init_machine = mx51_babbage_init,
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MACHINE_END
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