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4bd0481152
DMAEngine will be supported to this driver in the future. Then, both PIO and DMA data transfer method should be supported. But, the transfer function can returns the result immediately in PIO version, but it can't in DMA version. This patch divides data transfer functions into top/bottom half in preparation for DMAEngine support. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
231 lines
7.0 KiB
C
231 lines
7.0 KiB
C
/*
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* Renesas USB driver
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*
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* Copyright (C) 2011 Renesas Solutions Corp.
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* Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*
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*/
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#ifndef RENESAS_USB_DRIVER_H
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#define RENESAS_USB_DRIVER_H
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#include <linux/platform_device.h>
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#include <linux/usb/renesas_usbhs.h>
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struct usbhs_priv;
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#include "./mod.h"
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#include "./pipe.h"
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/*
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*
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* register define
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*
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*/
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#define SYSCFG 0x0000
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#define BUSWAIT 0x0002
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#define DVSTCTR 0x0008
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#define CFIFO 0x0014
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#define CFIFOSEL 0x0020
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#define CFIFOCTR 0x0022
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#define INTENB0 0x0030
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#define INTENB1 0x0032
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#define BRDYENB 0x0036
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#define NRDYENB 0x0038
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#define BEMPENB 0x003A
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#define INTSTS0 0x0040
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#define INTSTS1 0x0042
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#define BRDYSTS 0x0046
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#define NRDYSTS 0x0048
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#define BEMPSTS 0x004A
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#define FRMNUM 0x004C
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#define USBREQ 0x0054 /* USB request type register */
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#define USBVAL 0x0056 /* USB request value register */
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#define USBINDX 0x0058 /* USB request index register */
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#define USBLENG 0x005A /* USB request length register */
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#define DCPCFG 0x005C
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#define DCPMAXP 0x005E
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#define DCPCTR 0x0060
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#define PIPESEL 0x0064
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#define PIPECFG 0x0068
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#define PIPEBUF 0x006A
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#define PIPEMAXP 0x006C
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#define PIPEPERI 0x006E
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#define PIPEnCTR 0x0070
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/* SYSCFG */
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#define SCKE (1 << 10) /* USB Module Clock Enable */
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#define HSE (1 << 7) /* High-Speed Operation Enable */
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#define DCFM (1 << 6) /* Controller Function Select */
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#define DRPD (1 << 5) /* D+ Line/D- Line Resistance Control */
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#define DPRPU (1 << 4) /* D+ Line Resistance Control */
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#define USBE (1 << 0) /* USB Module Operation Enable */
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/* DVSTCTR */
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#define EXTLP (1 << 10) /* Controls the EXTLP pin output state */
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#define PWEN (1 << 9) /* Controls the PWEN pin output state */
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#define RHST (0x7) /* Reset Handshake */
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#define RHST_LOW_SPEED 1 /* Low-speed connection */
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#define RHST_FULL_SPEED 2 /* Full-speed connection */
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#define RHST_HIGH_SPEED 3 /* High-speed connection */
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/* CFIFOSEL */
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#define MBW_32 (0x2 << 10) /* CFIFO Port Access Bit Width */
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/* CFIFOCTR */
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#define BVAL (1 << 15) /* Buffer Memory Enable Flag */
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#define BCLR (1 << 14) /* CPU buffer clear */
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#define FRDY (1 << 13) /* FIFO Port Ready */
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#define DTLN_MASK (0x0FFF) /* Receive Data Length */
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/* INTENB0 */
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#define VBSE (1 << 15) /* Enable IRQ VBUS_0 and VBUSIN_0 */
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#define RSME (1 << 14) /* Enable IRQ Resume */
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#define SOFE (1 << 13) /* Enable IRQ Frame Number Update */
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#define DVSE (1 << 12) /* Enable IRQ Device State Transition */
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#define CTRE (1 << 11) /* Enable IRQ Control Stage Transition */
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#define BEMPE (1 << 10) /* Enable IRQ Buffer Empty */
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#define NRDYE (1 << 9) /* Enable IRQ Buffer Not Ready Response */
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#define BRDYE (1 << 8) /* Enable IRQ Buffer Ready */
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/* INTENB1 */
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#define BCHGE (1 << 14) /* USB Bus Change Interrupt Enable */
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#define DTCHE (1 << 12) /* Disconnection Detect Interrupt Enable */
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#define ATTCHE (1 << 11) /* Connection Detect Interrupt Enable */
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#define EOFERRE (1 << 6) /* EOF Error Detect Interrupt Enable */
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#define SIGNE (1 << 5) /* Setup Transaction Error Interrupt Enable */
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#define SACKE (1 << 4) /* Setup Transaction ACK Interrupt Enable */
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/* INTSTS0 */
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#define VBINT (1 << 15) /* VBUS0_0 and VBUS1_0 Interrupt Status */
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#define DVST (1 << 12) /* Device State Transition Interrupt Status */
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#define CTRT (1 << 11) /* Control Stage Interrupt Status */
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#define BEMP (1 << 10) /* Buffer Empty Interrupt Status */
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#define BRDY (1 << 8) /* Buffer Ready Interrupt Status */
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#define VBSTS (1 << 7) /* VBUS_0 and VBUSIN_0 Input Status */
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#define VALID (1 << 3) /* USB Request Receive */
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#define DVSQ_MASK (0x3 << 4) /* Device State */
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#define POWER_STATE (0 << 4)
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#define DEFAULT_STATE (1 << 4)
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#define ADDRESS_STATE (2 << 4)
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#define CONFIGURATION_STATE (3 << 4)
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#define CTSQ_MASK (0x7) /* Control Transfer Stage */
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#define IDLE_SETUP_STAGE 0 /* Idle stage or setup stage */
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#define READ_DATA_STAGE 1 /* Control read data stage */
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#define READ_STATUS_STAGE 2 /* Control read status stage */
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#define WRITE_DATA_STAGE 3 /* Control write data stage */
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#define WRITE_STATUS_STAGE 4 /* Control write status stage */
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#define NODATA_STATUS_STAGE 5 /* Control write NoData status stage */
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#define SEQUENCE_ERROR 6 /* Control transfer sequence error */
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/* PIPECFG */
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/* DCPCFG */
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#define TYPE_NONE (0 << 14) /* Transfer Type */
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#define TYPE_BULK (1 << 14)
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#define TYPE_INT (2 << 14)
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#define TYPE_ISO (3 << 14)
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#define DBLB (1 << 9) /* Double Buffer Mode */
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#define SHTNAK (1 << 7) /* Pipe Disable in Transfer End */
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#define DIR_OUT (1 << 4) /* Transfer Direction */
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/* PIPEMAXP */
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/* DCPMAXP */
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#define DEVSEL_MASK (0xF << 12) /* Device Select */
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#define DCP_MAXP_MASK (0x7F)
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#define PIPE_MAXP_MASK (0x7FF)
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/* PIPEBUF */
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#define BUFSIZE_SHIFT 10
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#define BUFSIZE_MASK (0x1F << BUFSIZE_SHIFT)
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#define BUFNMB_MASK (0xFF)
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/* PIPEnCTR */
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/* DCPCTR */
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#define BSTS (1 << 15) /* Buffer Status */
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#define CSSTS (1 << 12) /* CSSTS Status */
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#define SQCLR (1 << 8) /* Toggle Bit Clear */
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#define ACLRM (1 << 9) /* Buffer Auto-Clear Mode */
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#define PBUSY (1 << 5) /* Pipe Busy */
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#define PID_MASK (0x3) /* Response PID */
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#define PID_NAK 0
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#define PID_BUF 1
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#define PID_STALL10 2
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#define PID_STALL11 3
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#define CCPL (1 << 2) /* Control Transfer End Enable */
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/* FRMNUM */
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#define FRNM_MASK (0x7FF)
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/*
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* struct
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*/
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struct usbhs_priv {
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void __iomem *base;
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unsigned int irq;
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struct renesas_usbhs_platform_callback *pfunc;
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struct renesas_usbhs_driver_param *dparam;
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struct delayed_work notify_hotplug_work;
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struct platform_device *pdev;
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spinlock_t lock;
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u32 flags;
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/*
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* module control
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*/
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struct usbhs_mod_info mod_info;
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/*
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* pipe control
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*/
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struct usbhs_pipe_info pipe_info;
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};
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/*
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* common
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*/
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u16 usbhs_read(struct usbhs_priv *priv, u32 reg);
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void usbhs_write(struct usbhs_priv *priv, u32 reg, u16 data);
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void usbhs_bset(struct usbhs_priv *priv, u32 reg, u16 mask, u16 data);
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int usbhsc_drvcllbck_notify_hotplug(struct platform_device *pdev);
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/*
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* sysconfig
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*/
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void usbhs_sys_clock_ctrl(struct usbhs_priv *priv, int enable);
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void usbhs_sys_hispeed_ctrl(struct usbhs_priv *priv, int enable);
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void usbhs_sys_usb_ctrl(struct usbhs_priv *priv, int enable);
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void usbhs_sys_host_ctrl(struct usbhs_priv *priv, int enable);
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void usbhs_sys_function_ctrl(struct usbhs_priv *priv, int enable);
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/*
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* frame
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*/
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int usbhs_frame_get_num(struct usbhs_priv *priv);
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/*
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* data
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*/
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struct usbhs_priv *usbhs_pdev_to_priv(struct platform_device *pdev);
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#define usbhs_get_dparam(priv, param) (priv->dparam->param)
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#define usbhs_priv_to_pdev(priv) (priv->pdev)
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#define usbhs_priv_to_dev(priv) (&priv->pdev->dev)
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#define usbhs_priv_to_lock(priv) (&priv->lock)
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#endif /* RENESAS_USB_DRIVER_H */
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