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https://github.com/edk2-porting/linux-next.git
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8bb65fc06c
Revert changes introduced by commitf0fbe7bce7
("gpio: Move irqdomain into struct gpio_irq_chip") as they are not aplicable to this driver. Reported-by: Russell King - ARM Linux <linux@armlinux.org.uk> Fixes:f0fbe7bce7
("gpio: Move irqdomain into struct gpio_irq_chip") Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
186 lines
4.7 KiB
C
186 lines
4.7 KiB
C
/*
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* gpio-reg: single register individually fixed-direction GPIOs
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*
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* Copyright (C) 2016 Russell King
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*/
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#include <linux/gpio/driver.h>
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#include <linux/gpio/gpio-reg.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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struct gpio_reg {
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struct gpio_chip gc;
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spinlock_t lock;
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u32 direction;
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u32 out;
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void __iomem *reg;
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struct irq_domain *irqdomain;
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const int *irqs;
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};
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#define to_gpio_reg(x) container_of(x, struct gpio_reg, gc)
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static int gpio_reg_get_direction(struct gpio_chip *gc, unsigned offset)
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{
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struct gpio_reg *r = to_gpio_reg(gc);
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return r->direction & BIT(offset) ? 1 : 0;
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}
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static int gpio_reg_direction_output(struct gpio_chip *gc, unsigned offset,
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int value)
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{
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struct gpio_reg *r = to_gpio_reg(gc);
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if (r->direction & BIT(offset))
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return -ENOTSUPP;
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gc->set(gc, offset, value);
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return 0;
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}
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static int gpio_reg_direction_input(struct gpio_chip *gc, unsigned offset)
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{
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struct gpio_reg *r = to_gpio_reg(gc);
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return r->direction & BIT(offset) ? 0 : -ENOTSUPP;
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}
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static void gpio_reg_set(struct gpio_chip *gc, unsigned offset, int value)
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{
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struct gpio_reg *r = to_gpio_reg(gc);
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unsigned long flags;
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u32 val, mask = BIT(offset);
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spin_lock_irqsave(&r->lock, flags);
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val = r->out;
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if (value)
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val |= mask;
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else
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val &= ~mask;
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r->out = val;
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writel_relaxed(val, r->reg);
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spin_unlock_irqrestore(&r->lock, flags);
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}
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static int gpio_reg_get(struct gpio_chip *gc, unsigned offset)
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{
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struct gpio_reg *r = to_gpio_reg(gc);
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u32 val, mask = BIT(offset);
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if (r->direction & mask) {
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/*
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* double-read the value, some registers latch after the
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* first read.
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*/
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readl_relaxed(r->reg);
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val = readl_relaxed(r->reg);
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} else {
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val = r->out;
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}
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return !!(val & mask);
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}
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static void gpio_reg_set_multiple(struct gpio_chip *gc, unsigned long *mask,
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unsigned long *bits)
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{
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struct gpio_reg *r = to_gpio_reg(gc);
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unsigned long flags;
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spin_lock_irqsave(&r->lock, flags);
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r->out = (r->out & ~*mask) | (*bits & *mask);
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writel_relaxed(r->out, r->reg);
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spin_unlock_irqrestore(&r->lock, flags);
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}
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static int gpio_reg_to_irq(struct gpio_chip *gc, unsigned offset)
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{
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struct gpio_reg *r = to_gpio_reg(gc);
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int irq = r->irqs[offset];
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if (irq >= 0 && r->irqdomain)
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irq = irq_find_mapping(r->irqdomain, irq);
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return irq;
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}
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/**
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* gpio_reg_init - add a fixed in/out register as gpio
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* @dev: optional struct device associated with this register
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* @base: start gpio number, or -1 to allocate
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* @num: number of GPIOs, maximum 32
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* @label: GPIO chip label
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* @direction: bitmask of fixed direction, one per GPIO signal, 1 = in
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* @def_out: initial GPIO output value
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* @names: array of %num strings describing each GPIO signal or %NULL
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* @irqdom: irq domain or %NULL
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* @irqs: array of %num ints describing the interrupt mapping for each
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* GPIO signal, or %NULL. If @irqdom is %NULL, then this
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* describes the Linux interrupt number, otherwise it describes
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* the hardware interrupt number in the specified irq domain.
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*
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* Add a single-register GPIO device containing up to 32 GPIO signals,
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* where each GPIO has a fixed input or output configuration. Only
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* input GPIOs are assumed to be readable from the register, and only
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* then after a double-read. Output values are assumed not to be
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* readable.
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*/
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struct gpio_chip *gpio_reg_init(struct device *dev, void __iomem *reg,
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int base, int num, const char *label, u32 direction, u32 def_out,
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const char *const *names, struct irq_domain *irqdom, const int *irqs)
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{
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struct gpio_reg *r;
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int ret;
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if (dev)
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r = devm_kzalloc(dev, sizeof(*r), GFP_KERNEL);
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else
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r = kzalloc(sizeof(*r), GFP_KERNEL);
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if (!r)
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return ERR_PTR(-ENOMEM);
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spin_lock_init(&r->lock);
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r->gc.label = label;
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r->gc.get_direction = gpio_reg_get_direction;
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r->gc.direction_input = gpio_reg_direction_input;
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r->gc.direction_output = gpio_reg_direction_output;
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r->gc.set = gpio_reg_set;
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r->gc.get = gpio_reg_get;
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r->gc.set_multiple = gpio_reg_set_multiple;
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if (irqs)
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r->gc.to_irq = gpio_reg_to_irq;
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r->gc.base = base;
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r->gc.ngpio = num;
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r->gc.names = names;
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r->direction = direction;
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r->out = def_out;
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r->reg = reg;
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r->irqs = irqs;
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if (dev)
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ret = devm_gpiochip_add_data(dev, &r->gc, r);
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else
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ret = gpiochip_add_data(&r->gc, r);
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return ret ? ERR_PTR(ret) : &r->gc;
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}
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int gpio_reg_resume(struct gpio_chip *gc)
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{
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struct gpio_reg *r = to_gpio_reg(gc);
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unsigned long flags;
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spin_lock_irqsave(&r->lock, flags);
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writel_relaxed(r->out, r->reg);
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spin_unlock_irqrestore(&r->lock, flags);
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return 0;
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}
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