mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-25 21:54:06 +08:00
1f6ccfff63
The notable features are:
- SMP configurations of upto 4 cores with coherency
- Optional L2 Cache and IO-Coherency
- Revised Interrupt Architecture (multiple priorites, reg banks,
auto stack switch, auto regfile save/restore)
- MMUv4 (PIPT dcache, Huge Pages)
- Instructions for
* 64bit load/store: LDD, STD
* Hardware assisted divide/remainder: DIV, REM
* Function prologue/epilogue: ENTER_S, LEAVE_S
* IRQ enable/disable: CLRI, SETI
* pop count: FFS, FLS
* SETcc, BMSKN, XBFU...
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
131 lines
3.5 KiB
ArmAsm
131 lines
3.5 KiB
ArmAsm
/*
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* ARC CPU startup Code
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*
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* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Vineetg: Dec 2007
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* -Check if we are running on Simulator or on real hardware
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* to skip certain things during boot on simulator
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*/
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#include <linux/linkage.h>
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#include <asm/asm-offsets.h>
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#include <asm/entry.h>
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#include <asm/arcregs.h>
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#include <asm/cache.h>
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.macro CPU_EARLY_SETUP
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; Setting up Vectror Table (in case exception happens in early boot
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sr @_int_vec_base_lds, [AUX_INTR_VEC_BASE]
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; Disable I-cache/D-cache if kernel so configured
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lr r5, [ARC_REG_IC_BCR]
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breq r5, 0, 1f ; I$ doesn't exist
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lr r5, [ARC_REG_IC_CTRL]
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#ifdef CONFIG_ARC_HAS_ICACHE
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bclr r5, r5, 0 ; 0 - Enable, 1 is Disable
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#else
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bset r5, r5, 0 ; I$ exists, but is not used
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#endif
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sr r5, [ARC_REG_IC_CTRL]
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1:
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lr r5, [ARC_REG_DC_BCR]
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breq r5, 0, 1f ; D$ doesn't exist
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lr r5, [ARC_REG_DC_CTRL]
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bclr r5, r5, 6 ; Invalidate (discard w/o wback)
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#ifdef CONFIG_ARC_HAS_DCACHE
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bclr r5, r5, 0 ; Enable (+Inv)
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#else
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bset r5, r5, 0 ; Disable (+Inv)
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#endif
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sr r5, [ARC_REG_DC_CTRL]
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1:
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.endm
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.section .init.text, "ax",@progbits
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.type stext, @function
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.globl stext
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stext:
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;-------------------------------------------------------------------
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; Don't clobber r0-r2 yet. It might have bootloader provided info
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;-------------------------------------------------------------------
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CPU_EARLY_SETUP
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#ifdef CONFIG_SMP
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; Ensure Boot (Master) proceeds. Others wait in platform dependent way
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; IDENTITY Reg [ 3 2 1 0 ]
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; (cpu-id) ^^^ => Zero for UP ARC700
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; => #Core-ID if SMP (Master 0)
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; Note that non-boot CPUs might not land here if halt-on-reset and
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; instead breath life from @first_lines_of_secondary, but we still
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; need to make sure only boot cpu takes this path.
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GET_CPU_ID r5
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cmp r5, 0
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mov.ne r0, r5
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jne arc_platform_smp_wait_to_boot
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#endif
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; Clear BSS before updating any globals
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; XXX: use ZOL here
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mov r5, __bss_start
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sub r6, __bss_stop, r5
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lsr.f lp_count, r6, 2
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lpnz 1f
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st.ab 0, [r5, 4]
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1:
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#ifdef CONFIG_ARC_UBOOT_SUPPORT
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; Uboot - kernel ABI
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; r0 = [0] No uboot interaction, [1] cmdline in r2, [2] DTB in r2
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; r1 = magic number (board identity, unused as of now
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; r2 = pointer to uboot provided cmdline or external DTB in mem
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; These are handled later in setup_arch()
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st r0, [@uboot_tag]
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st r2, [@uboot_arg]
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#endif
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; setup "current" tsk and optionally cache it in dedicated r25
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mov r9, @init_task
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SET_CURR_TASK_ON_CPU r9, r0 ; r9 = tsk, r0 = scratch
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; setup stack (fp, sp)
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mov fp, 0
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; tsk->thread_info is really a PAGE, whose bottom hoists stack
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GET_TSK_STACK_BASE r9, sp ; r9 = tsk, sp = stack base(output)
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j start_kernel ; "C" entry point
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#ifdef CONFIG_SMP
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;----------------------------------------------------------------
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; First lines of code run by secondary before jumping to 'C'
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;----------------------------------------------------------------
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.section .text, "ax",@progbits
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.type first_lines_of_secondary, @function
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.globl first_lines_of_secondary
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first_lines_of_secondary:
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CPU_EARLY_SETUP
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; setup per-cpu idle task as "current" on this CPU
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ld r0, [@secondary_idle_tsk]
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SET_CURR_TASK_ON_CPU r0, r1
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; setup stack (fp, sp)
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mov fp, 0
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; set it's stack base to tsk->thread_info bottom
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GET_TSK_STACK_BASE r0, sp
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j start_kernel_secondary
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#endif
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