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0fabe43f3f
The pin controller has been updated in the Amlogic Meson AXG series, which use continuous 4-bit register to select function for each pin. In order to support this, a new pinmux operations "meson_axg_pmx_ops" has been added. Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> Reviewed-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
63 lines
1.3 KiB
C
63 lines
1.3 KiB
C
/*
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* Copyright (c) 2017 Baylibre SAS.
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* Author: Jerome Brunet <jbrunet@baylibre.com>
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*
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* Copyright (c) 2017 Amlogic, Inc. All rights reserved.
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* Author: Xingyu Chen <xingyu.chen@amlogic.com>
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*
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* SPDX-License-Identifier: (GPL-2.0+ or MIT)
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*/
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struct meson_pmx_bank {
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const char *name;
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unsigned int first;
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unsigned int last;
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unsigned int reg;
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unsigned int offset;
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};
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struct meson_axg_pmx_data {
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struct meson_pmx_bank *pmx_banks;
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unsigned int num_pmx_banks;
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};
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#define BANK_PMX(n, f, l, r, o) \
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{ \
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.name = n, \
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.first = f, \
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.last = l, \
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.reg = r, \
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.offset = o, \
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}
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struct meson_pmx_axg_data {
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unsigned int func;
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};
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#define PMX_DATA(f) \
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{ \
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.func = f, \
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}
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#define GROUP(grp, f) \
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{ \
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.name = #grp, \
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.pins = grp ## _pins, \
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.num_pins = ARRAY_SIZE(grp ## _pins), \
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.data = (const struct meson_pmx_axg_data[]){ \
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PMX_DATA(f), \
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}, \
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}
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#define GPIO_GROUP(gpio) \
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{ \
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.name = #gpio, \
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.pins = (const unsigned int[]){ gpio }, \
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.num_pins = 1, \
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.data = (const struct meson_pmx_axg_data[]){ \
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PMX_DATA(0), \
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}, \
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}
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extern const struct pinmux_ops meson_axg_pmx_ops;
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