mirror of
https://github.com/edk2-porting/linux-next.git
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18a8d49973
enhancements and fixes mostly for ARM32, ARM64, MIPS and Power-based
devices. Additionaly the framework core underwent a bit of surgery with
two major changes. The boundary between the clock core and clock
providers (e.g clock drivers) is now more well defined with dedicated
provider helper functions. struct clk no longer maps 1:1 with the
hardware clock but is a true per-user cookie which helps us tracker
users of hardware clocks and debug bad behavior. The second major change
is the addition of rate constraints for clocks. Rate ranges are now
supported which are analogous to the voltage ranges in the regulator
framework. Unfortunately these changes to the core created some
breakeage. We think we fixed it all up but for this reason there are
lots of last minute commits trying to undo the damage.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJU54D5AAoJEDqPOy9afJhJs6AQAK5YuUwjDchdpNZx9p7OnT1q
+poehuUwE/gYjmdACqYFyaPrI/9f43iNCfFAgKGLQqmB5ZK4sm4ktzfBEhjWINR2
iiCx9QYMQVGiKwC8KU0ddeBciglE2b/DwxB45m9TsJEjowucUeBzwLEIj5DsGxf7
teXRoOWgXdz1MkQJ4pnA09Q3qEPQgmu8prhMfka/v75/yn7nb9VWiJ6seR2GqTKY
sIKL9WbKjN4AzctggdqHnMSIqZoq6vew850bv2C1fPn7GiYFQfWW+jvMlVY40dp8
nNa2ixSQSIXVw4fCtZhTIZcIvZ8puc7WVLcl8fz3mUe3VJn1VaGs0E+Yd3GexpIV
7bwkTOIdS8gSRlsUaIPiMnUob5TUMmMqjF4KIh/AhP4dYrmVbU7Ie8ccvSxe31Ku
lK7ww6BFv3KweTnW/58856ZXDlXLC6x3KT+Fw58L23VhPToFgYOdTxn8AVtE/LKP
YR3UnY9BqFx6WHXVoNvg3Piyej7RH8fYmE9om8tyWc/Ab8Eo501SHs9l3b2J8snf
w/5STd2CYxyKf1/9JLGnBvGo754O9NvdzBttRlygB14gCCtS/SDk/ELG2Ae+/a9P
YgRk2+257h8PMD3qlp94dLidEZN4kYxP/J6oj0t1/TIkERWfZjzkg5tKn3/hEcU9
qM97ZBTplTm6FM+Dt/Vk
=zCVK
-----END PGP SIGNATURE-----
Merge tag 'clk-for-linus-3.20' of git://git.linaro.org/people/mike.turquette/linux
Pull clock framework updates from Mike Turquette:
"The clock framework changes contain the usual driver additions,
enhancements and fixes mostly for ARM32, ARM64, MIPS and Power-based
devices.
Additionally the framework core underwent a bit of surgery with two
major changes:
- The boundary between the clock core and clock providers (e.g clock
drivers) is now more well defined with dedicated provider helper
functions. struct clk no longer maps 1:1 with the hardware clock
but is a true per-user cookie which helps us tracker users of
hardware clocks and debug bad behavior.
- The addition of rate constraints for clocks. Rate ranges are now
supported which are analogous to the voltage ranges in the
regulator framework.
Unfortunately these changes to the core created some breakeage. We
think we fixed it all up but for this reason there are lots of last
minute commits trying to undo the damage"
* tag 'clk-for-linus-3.20' of git://git.linaro.org/people/mike.turquette/linux: (113 commits)
clk: Only recalculate the rate if needed
Revert "clk: mxs: Fix invalid 32-bit access to frac registers"
clk: qoriq: Add support for the platform PLL
powerpc/corenet: Enable CLK_QORIQ
clk: Replace explicit clk assignment with __clk_hw_set_clk
clk: Add __clk_hw_set_clk helper function
clk: Don't dereference parent clock if is NULL
MIPS: Alchemy: Remove bogus args from alchemy_clk_fgcs_detr
clkdev: Always allocate a struct clk and call __clk_get() w/ CCF
clk: shmobile: div6: Avoid division by zero in .round_rate()
clk: mxs: Fix invalid 32-bit access to frac registers
clk: omap: compile legacy omap3 clocks conditionally
clkdev: Export clk_register_clkdev
clk: Add rate constraints to clocks
clk: remove clk-private.h
pci: xgene: do not use clk-private.h
arm: omap2+ remove dead clock code
clk: Make clk API return per-user struct clk instances
clk: tegra: Define PLLD_DSI and remove dsia(b)_mux
clk: tegra: Add support for the Tegra132 CAR IP block
...
154 lines
4.1 KiB
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154 lines
4.1 KiB
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config CLKDEV_LOOKUP
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bool
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select HAVE_CLK
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config HAVE_CLK_PREPARE
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bool
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config HAVE_MACH_CLKDEV
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bool
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config COMMON_CLK
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bool
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select HAVE_CLK_PREPARE
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select CLKDEV_LOOKUP
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select SRCU
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---help---
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The common clock framework is a single definition of struct
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clk, useful across many platforms, as well as an
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implementation of the clock API in include/linux/clk.h.
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Architectures utilizing the common struct clk should select
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this option.
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menu "Common Clock Framework"
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depends on COMMON_CLK
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config COMMON_CLK_WM831X
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tristate "Clock driver for WM831x/2x PMICs"
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depends on MFD_WM831X
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---help---
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Supports the clocking subsystem of the WM831x/2x series of
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PMICs from Wolfson Microelectronics.
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source "drivers/clk/versatile/Kconfig"
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config COMMON_CLK_MAX_GEN
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bool
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config COMMON_CLK_MAX77686
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tristate "Clock driver for Maxim 77686 MFD"
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depends on MFD_MAX77686
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select COMMON_CLK_MAX_GEN
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---help---
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This driver supports Maxim 77686 crystal oscillator clock.
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config COMMON_CLK_MAX77802
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tristate "Clock driver for Maxim 77802 PMIC"
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depends on MFD_MAX77686
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select COMMON_CLK_MAX_GEN
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---help---
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This driver supports Maxim 77802 crystal oscillator clock.
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config COMMON_CLK_RK808
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tristate "Clock driver for RK808"
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depends on MFD_RK808
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---help---
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This driver supports RK808 crystal oscillator clock. These
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multi-function devices have two fixed-rate oscillators,
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clocked at 32KHz each. Clkout1 is always on, Clkout2 can off
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by control register.
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config COMMON_CLK_SI5351
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tristate "Clock driver for SiLabs 5351A/B/C"
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depends on I2C
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select REGMAP_I2C
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select RATIONAL
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---help---
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This driver supports Silicon Labs 5351A/B/C programmable clock
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generators.
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config COMMON_CLK_SI570
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tristate "Clock driver for SiLabs 570 and compatible devices"
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depends on I2C
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depends on OF
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select REGMAP_I2C
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help
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---help---
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This driver supports Silicon Labs 570/571/598/599 programmable
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clock generators.
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config COMMON_CLK_S2MPS11
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tristate "Clock driver for S2MPS1X/S5M8767 MFD"
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depends on MFD_SEC_CORE
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---help---
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This driver supports S2MPS11/S2MPS14/S5M8767 crystal oscillator
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clock. These multi-function devices have two (S2MPS14) or three
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(S2MPS11, S5M8767) fixed-rate oscillators, clocked at 32KHz each.
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config CLK_TWL6040
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tristate "External McPDM functional clock from twl6040"
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depends on TWL6040_CORE
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---help---
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Enable the external functional clock support on OMAP4+ platforms for
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McPDM. McPDM module is using the external bit clock on the McPDM bus
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as functional clock.
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config COMMON_CLK_AXI_CLKGEN
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tristate "AXI clkgen driver"
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depends on ARCH_ZYNQ || MICROBLAZE
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help
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---help---
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Support for the Analog Devices axi-clkgen pcore clock generator for Xilinx
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FPGAs. It is commonly used in Analog Devices' reference designs.
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config CLK_QORIQ
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bool "Clock driver for Freescale QorIQ platforms"
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depends on (PPC_E500MC || ARM) && OF
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---help---
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This adds the clock driver support for Freescale QorIQ platforms
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using common clock framework.
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config COMMON_CLK_XGENE
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bool "Clock driver for APM XGene SoC"
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default y
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depends on ARM64
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---help---
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Sypport for the APM X-Gene SoC reference, PLL, and device clocks.
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config COMMON_CLK_KEYSTONE
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tristate "Clock drivers for Keystone based SOCs"
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depends on ARCH_KEYSTONE && OF
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---help---
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Supports clock drivers for Keystone based SOCs. These SOCs have local
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a power sleep control module that gate the clock to the IPs and PLLs.
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config COMMON_CLK_PALMAS
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tristate "Clock driver for TI Palmas devices"
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depends on MFD_PALMAS
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---help---
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This driver supports TI Palmas devices 32KHz output KG and KG_AUDIO
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using common clock framework.
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config COMMON_CLK_PXA
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def_bool COMMON_CLK && ARCH_PXA
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---help---
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Sypport for the Marvell PXA SoC.
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config COMMON_CLK_CDCE706
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tristate "Clock driver for TI CDCE706 clock synthesizer"
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depends on I2C
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select REGMAP_I2C
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select RATIONAL
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---help---
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This driver supports TI CDCE706 programmable 3-PLL clock synthesizer.
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source "drivers/clk/qcom/Kconfig"
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endmenu
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source "drivers/clk/bcm/Kconfig"
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source "drivers/clk/mvebu/Kconfig"
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source "drivers/clk/samsung/Kconfig"
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