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4a6dae6d38
Introduce an atomic_cmpxchg operation. Signed-off-by: Nick Piggin <npiggin@suse.de> Cc: "Paul E. McKenney" <paulmck@us.ibm.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
382 lines
7.1 KiB
C
382 lines
7.1 KiB
C
#ifndef _ASM_POWERPC_ATOMIC_H_
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#define _ASM_POWERPC_ATOMIC_H_
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/*
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* PowerPC atomic operations
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*/
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typedef struct { volatile int counter; } atomic_t;
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#ifdef __KERNEL__
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#include <asm/synch.h>
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#include <asm/asm-compat.h>
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#define ATOMIC_INIT(i) { (i) }
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#define atomic_read(v) ((v)->counter)
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#define atomic_set(v,i) (((v)->counter) = (i))
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static __inline__ void atomic_add(int a, atomic_t *v)
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{
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int t;
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__asm__ __volatile__(
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"1: lwarx %0,0,%3 # atomic_add\n\
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add %0,%2,%0\n"
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PPC405_ERR77(0,%3)
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" stwcx. %0,0,%3 \n\
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bne- 1b"
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: "=&r" (t), "=m" (v->counter)
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: "r" (a), "r" (&v->counter), "m" (v->counter)
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: "cc");
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}
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static __inline__ int atomic_add_return(int a, atomic_t *v)
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{
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int t;
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__asm__ __volatile__(
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EIEIO_ON_SMP
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"1: lwarx %0,0,%2 # atomic_add_return\n\
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add %0,%1,%0\n"
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PPC405_ERR77(0,%2)
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" stwcx. %0,0,%2 \n\
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bne- 1b"
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ISYNC_ON_SMP
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: "=&r" (t)
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: "r" (a), "r" (&v->counter)
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: "cc", "memory");
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return t;
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}
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#define atomic_add_negative(a, v) (atomic_add_return((a), (v)) < 0)
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static __inline__ void atomic_sub(int a, atomic_t *v)
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{
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int t;
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__asm__ __volatile__(
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"1: lwarx %0,0,%3 # atomic_sub\n\
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subf %0,%2,%0\n"
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PPC405_ERR77(0,%3)
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" stwcx. %0,0,%3 \n\
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bne- 1b"
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: "=&r" (t), "=m" (v->counter)
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: "r" (a), "r" (&v->counter), "m" (v->counter)
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: "cc");
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}
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static __inline__ int atomic_sub_return(int a, atomic_t *v)
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{
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int t;
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__asm__ __volatile__(
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EIEIO_ON_SMP
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"1: lwarx %0,0,%2 # atomic_sub_return\n\
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subf %0,%1,%0\n"
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PPC405_ERR77(0,%2)
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" stwcx. %0,0,%2 \n\
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bne- 1b"
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ISYNC_ON_SMP
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: "=&r" (t)
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: "r" (a), "r" (&v->counter)
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: "cc", "memory");
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return t;
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}
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static __inline__ void atomic_inc(atomic_t *v)
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{
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int t;
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__asm__ __volatile__(
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"1: lwarx %0,0,%2 # atomic_inc\n\
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addic %0,%0,1\n"
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PPC405_ERR77(0,%2)
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" stwcx. %0,0,%2 \n\
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bne- 1b"
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: "=&r" (t), "=m" (v->counter)
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: "r" (&v->counter), "m" (v->counter)
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: "cc");
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}
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static __inline__ int atomic_inc_return(atomic_t *v)
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{
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int t;
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__asm__ __volatile__(
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EIEIO_ON_SMP
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"1: lwarx %0,0,%1 # atomic_inc_return\n\
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addic %0,%0,1\n"
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PPC405_ERR77(0,%1)
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" stwcx. %0,0,%1 \n\
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bne- 1b"
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ISYNC_ON_SMP
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: "=&r" (t)
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: "r" (&v->counter)
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: "cc", "memory");
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return t;
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}
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/*
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* atomic_inc_and_test - increment and test
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* @v: pointer of type atomic_t
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*
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* Atomically increments @v by 1
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* and returns true if the result is zero, or false for all
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* other cases.
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*/
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#define atomic_inc_and_test(v) (atomic_inc_return(v) == 0)
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static __inline__ void atomic_dec(atomic_t *v)
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{
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int t;
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__asm__ __volatile__(
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"1: lwarx %0,0,%2 # atomic_dec\n\
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addic %0,%0,-1\n"
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PPC405_ERR77(0,%2)\
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" stwcx. %0,0,%2\n\
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bne- 1b"
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: "=&r" (t), "=m" (v->counter)
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: "r" (&v->counter), "m" (v->counter)
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: "cc");
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}
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static __inline__ int atomic_dec_return(atomic_t *v)
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{
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int t;
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__asm__ __volatile__(
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EIEIO_ON_SMP
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"1: lwarx %0,0,%1 # atomic_dec_return\n\
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addic %0,%0,-1\n"
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PPC405_ERR77(0,%1)
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" stwcx. %0,0,%1\n\
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bne- 1b"
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ISYNC_ON_SMP
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: "=&r" (t)
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: "r" (&v->counter)
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: "cc", "memory");
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return t;
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}
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#define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n)))
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#define atomic_sub_and_test(a, v) (atomic_sub_return((a), (v)) == 0)
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#define atomic_dec_and_test(v) (atomic_dec_return((v)) == 0)
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/*
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* Atomically test *v and decrement if it is greater than 0.
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* The function returns the old value of *v minus 1.
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*/
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static __inline__ int atomic_dec_if_positive(atomic_t *v)
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{
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int t;
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__asm__ __volatile__(
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EIEIO_ON_SMP
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"1: lwarx %0,0,%1 # atomic_dec_if_positive\n\
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addic. %0,%0,-1\n\
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blt- 2f\n"
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PPC405_ERR77(0,%1)
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" stwcx. %0,0,%1\n\
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bne- 1b"
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ISYNC_ON_SMP
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"\n\
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2:" : "=&r" (t)
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: "r" (&v->counter)
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: "cc", "memory");
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return t;
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}
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#define smp_mb__before_atomic_dec() smp_mb()
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#define smp_mb__after_atomic_dec() smp_mb()
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#define smp_mb__before_atomic_inc() smp_mb()
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#define smp_mb__after_atomic_inc() smp_mb()
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#ifdef __powerpc64__
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typedef struct { volatile long counter; } atomic64_t;
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#define ATOMIC64_INIT(i) { (i) }
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#define atomic64_read(v) ((v)->counter)
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#define atomic64_set(v,i) (((v)->counter) = (i))
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static __inline__ void atomic64_add(long a, atomic64_t *v)
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{
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long t;
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__asm__ __volatile__(
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"1: ldarx %0,0,%3 # atomic64_add\n\
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add %0,%2,%0\n\
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stdcx. %0,0,%3 \n\
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bne- 1b"
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: "=&r" (t), "=m" (v->counter)
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: "r" (a), "r" (&v->counter), "m" (v->counter)
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: "cc");
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}
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static __inline__ long atomic64_add_return(long a, atomic64_t *v)
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{
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long t;
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__asm__ __volatile__(
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EIEIO_ON_SMP
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"1: ldarx %0,0,%2 # atomic64_add_return\n\
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add %0,%1,%0\n\
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stdcx. %0,0,%2 \n\
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bne- 1b"
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ISYNC_ON_SMP
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: "=&r" (t)
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: "r" (a), "r" (&v->counter)
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: "cc", "memory");
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return t;
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}
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#define atomic64_add_negative(a, v) (atomic64_add_return((a), (v)) < 0)
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static __inline__ void atomic64_sub(long a, atomic64_t *v)
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{
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long t;
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__asm__ __volatile__(
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"1: ldarx %0,0,%3 # atomic64_sub\n\
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subf %0,%2,%0\n\
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stdcx. %0,0,%3 \n\
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bne- 1b"
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: "=&r" (t), "=m" (v->counter)
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: "r" (a), "r" (&v->counter), "m" (v->counter)
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: "cc");
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}
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static __inline__ long atomic64_sub_return(long a, atomic64_t *v)
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{
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long t;
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__asm__ __volatile__(
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EIEIO_ON_SMP
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"1: ldarx %0,0,%2 # atomic64_sub_return\n\
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subf %0,%1,%0\n\
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stdcx. %0,0,%2 \n\
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bne- 1b"
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ISYNC_ON_SMP
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: "=&r" (t)
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: "r" (a), "r" (&v->counter)
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: "cc", "memory");
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return t;
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}
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static __inline__ void atomic64_inc(atomic64_t *v)
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{
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long t;
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__asm__ __volatile__(
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"1: ldarx %0,0,%2 # atomic64_inc\n\
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addic %0,%0,1\n\
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stdcx. %0,0,%2 \n\
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bne- 1b"
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: "=&r" (t), "=m" (v->counter)
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: "r" (&v->counter), "m" (v->counter)
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: "cc");
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}
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static __inline__ long atomic64_inc_return(atomic64_t *v)
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{
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long t;
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__asm__ __volatile__(
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EIEIO_ON_SMP
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"1: ldarx %0,0,%1 # atomic64_inc_return\n\
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addic %0,%0,1\n\
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stdcx. %0,0,%1 \n\
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bne- 1b"
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ISYNC_ON_SMP
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: "=&r" (t)
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: "r" (&v->counter)
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: "cc", "memory");
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return t;
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}
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/*
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* atomic64_inc_and_test - increment and test
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* @v: pointer of type atomic64_t
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*
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* Atomically increments @v by 1
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* and returns true if the result is zero, or false for all
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* other cases.
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*/
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#define atomic64_inc_and_test(v) (atomic64_inc_return(v) == 0)
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static __inline__ void atomic64_dec(atomic64_t *v)
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{
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long t;
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__asm__ __volatile__(
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"1: ldarx %0,0,%2 # atomic64_dec\n\
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addic %0,%0,-1\n\
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stdcx. %0,0,%2\n\
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bne- 1b"
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: "=&r" (t), "=m" (v->counter)
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: "r" (&v->counter), "m" (v->counter)
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: "cc");
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}
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static __inline__ long atomic64_dec_return(atomic64_t *v)
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{
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long t;
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__asm__ __volatile__(
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EIEIO_ON_SMP
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"1: ldarx %0,0,%1 # atomic64_dec_return\n\
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addic %0,%0,-1\n\
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stdcx. %0,0,%1\n\
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bne- 1b"
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ISYNC_ON_SMP
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: "=&r" (t)
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: "r" (&v->counter)
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: "cc", "memory");
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return t;
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}
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#define atomic64_sub_and_test(a, v) (atomic64_sub_return((a), (v)) == 0)
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#define atomic64_dec_and_test(v) (atomic64_dec_return((v)) == 0)
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/*
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* Atomically test *v and decrement if it is greater than 0.
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* The function returns the old value of *v minus 1.
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*/
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static __inline__ long atomic64_dec_if_positive(atomic64_t *v)
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{
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long t;
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__asm__ __volatile__(
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EIEIO_ON_SMP
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"1: ldarx %0,0,%1 # atomic64_dec_if_positive\n\
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addic. %0,%0,-1\n\
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blt- 2f\n\
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stdcx. %0,0,%1\n\
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bne- 1b"
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ISYNC_ON_SMP
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"\n\
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2:" : "=&r" (t)
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: "r" (&v->counter)
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: "cc", "memory");
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return t;
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}
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#endif /* __powerpc64__ */
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#endif /* __KERNEL__ */
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#endif /* _ASM_POWERPC_ATOMIC_H_ */
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