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b3410e5f4b
Use the new handle_domain_irq method to handle interrupts. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Shawn Guo <shawn.guo@freescale.com> Link: https://lkml.kernel.org/r/1409047421-27649-10-git-send-email-marc.zyngier@arm.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
115 lines
3.3 KiB
C
115 lines
3.3 KiB
C
/*
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* Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/stmp_device.h>
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#include <asm/exception.h>
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#include "irqchip.h"
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#define HW_ICOLL_VECTOR 0x0000
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#define HW_ICOLL_LEVELACK 0x0010
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#define HW_ICOLL_CTRL 0x0020
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#define HW_ICOLL_STAT_OFFSET 0x0070
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#define HW_ICOLL_INTERRUPTn_SET(n) (0x0124 + (n) * 0x10)
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#define HW_ICOLL_INTERRUPTn_CLR(n) (0x0128 + (n) * 0x10)
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#define BM_ICOLL_INTERRUPTn_ENABLE 0x00000004
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#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0 0x1
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#define ICOLL_NUM_IRQS 128
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static void __iomem *icoll_base;
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static struct irq_domain *icoll_domain;
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static void icoll_ack_irq(struct irq_data *d)
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{
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/*
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* The Interrupt Collector is able to prioritize irqs.
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* Currently only level 0 is used. So acking can use
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* BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0 unconditionally.
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*/
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__raw_writel(BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0,
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icoll_base + HW_ICOLL_LEVELACK);
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}
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static void icoll_mask_irq(struct irq_data *d)
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{
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__raw_writel(BM_ICOLL_INTERRUPTn_ENABLE,
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icoll_base + HW_ICOLL_INTERRUPTn_CLR(d->hwirq));
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}
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static void icoll_unmask_irq(struct irq_data *d)
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{
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__raw_writel(BM_ICOLL_INTERRUPTn_ENABLE,
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icoll_base + HW_ICOLL_INTERRUPTn_SET(d->hwirq));
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}
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static struct irq_chip mxs_icoll_chip = {
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.irq_ack = icoll_ack_irq,
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.irq_mask = icoll_mask_irq,
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.irq_unmask = icoll_unmask_irq,
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};
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asmlinkage void __exception_irq_entry icoll_handle_irq(struct pt_regs *regs)
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{
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u32 irqnr;
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irqnr = __raw_readl(icoll_base + HW_ICOLL_STAT_OFFSET);
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__raw_writel(irqnr, icoll_base + HW_ICOLL_VECTOR);
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handle_domain_irq(icoll_domain, irqnr, regs);
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}
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static int icoll_irq_domain_map(struct irq_domain *d, unsigned int virq,
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irq_hw_number_t hw)
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{
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irq_set_chip_and_handler(virq, &mxs_icoll_chip, handle_level_irq);
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set_irq_flags(virq, IRQF_VALID);
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return 0;
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}
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static struct irq_domain_ops icoll_irq_domain_ops = {
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.map = icoll_irq_domain_map,
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.xlate = irq_domain_xlate_onecell,
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};
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static int __init icoll_of_init(struct device_node *np,
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struct device_node *interrupt_parent)
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{
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icoll_base = of_iomap(np, 0);
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WARN_ON(!icoll_base);
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/*
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* Interrupt Collector reset, which initializes the priority
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* for each irq to level 0.
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*/
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stmp_reset_block(icoll_base + HW_ICOLL_CTRL);
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icoll_domain = irq_domain_add_linear(np, ICOLL_NUM_IRQS,
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&icoll_irq_domain_ops, NULL);
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return icoll_domain ? 0 : -ENODEV;
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}
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IRQCHIP_DECLARE(mxs, "fsl,icoll", icoll_of_init);
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