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0ea8ce61cb
Add some basic documentation for LoongArch. LoongArch is a new RISC ISA, which is a bit like MIPS or RISC-V. LoongArch includes a reduced 32-bit version (LA32R), a standard 32-bit version (LA32S) and a 64-bit version (LA64). Tested-by: Bagas Sanjaya <bagasdotme@gmail.com> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Co-developed-by: WANG Xuerui <git@xen0n.name> Signed-off-by: WANG Xuerui <git@xen0n.name> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
29 lines
442 B
ReStructuredText
29 lines
442 B
ReStructuredText
.. SPDX-License-Identifier: GPL-2.0
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CPU Architectures
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=================
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These books provide programming details about architecture-specific
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implementation.
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.. toctree::
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:maxdepth: 2
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arc/index
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arm/index
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arm64/index
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ia64/index
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loongarch/index
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m68k/index
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mips/index
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nios2/index
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openrisc/index
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parisc/index
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powerpc/index
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riscv/index
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s390/index
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sh/index
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sparc/index
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x86/index
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xtensa/index
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