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981 lines
25 KiB
C
981 lines
25 KiB
C
/*
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* arch/arm/mm/cache-l2x0.c - L210/L220 cache controller support
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*
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* Copyright (C) 2007 ARM Limited
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/spinlock.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <asm/cacheflush.h>
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#include <asm/hardware/cache-l2x0.h>
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#include "cache-aurora-l2.h"
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#define CACHE_LINE_SIZE 32
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static void __iomem *l2x0_base;
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static DEFINE_RAW_SPINLOCK(l2x0_lock);
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static u32 l2x0_way_mask; /* Bitmask of active ways */
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static u32 l2x0_size;
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static unsigned long sync_reg_offset = L2X0_CACHE_SYNC;
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/* Aurora don't have the cache ID register available, so we have to
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* pass it though the device tree */
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static u32 cache_id_part_number_from_dt;
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struct l2x0_regs l2x0_saved_regs;
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struct l2x0_of_data {
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void (*setup)(const struct device_node *, u32 *, u32 *);
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void (*save)(void);
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struct outer_cache_fns outer_cache;
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};
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static bool of_init = false;
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static inline void cache_wait_way(void __iomem *reg, unsigned long mask)
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{
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/* wait for cache operation by line or way to complete */
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while (readl_relaxed(reg) & mask)
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cpu_relax();
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}
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#ifdef CONFIG_CACHE_PL310
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static inline void cache_wait(void __iomem *reg, unsigned long mask)
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{
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/* cache operations by line are atomic on PL310 */
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}
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#else
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#define cache_wait cache_wait_way
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#endif
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static inline void cache_sync(void)
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{
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void __iomem *base = l2x0_base;
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writel_relaxed(0, base + sync_reg_offset);
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cache_wait(base + L2X0_CACHE_SYNC, 1);
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}
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static inline void l2x0_clean_line(unsigned long addr)
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{
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void __iomem *base = l2x0_base;
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cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
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writel_relaxed(addr, base + L2X0_CLEAN_LINE_PA);
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}
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static inline void l2x0_inv_line(unsigned long addr)
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{
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void __iomem *base = l2x0_base;
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cache_wait(base + L2X0_INV_LINE_PA, 1);
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writel_relaxed(addr, base + L2X0_INV_LINE_PA);
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}
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#if defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915)
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static inline void debug_writel(unsigned long val)
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{
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if (outer_cache.set_debug)
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outer_cache.set_debug(val);
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}
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static void pl310_set_debug(unsigned long val)
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{
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writel_relaxed(val, l2x0_base + L2X0_DEBUG_CTRL);
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}
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#else
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/* Optimised out for non-errata case */
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static inline void debug_writel(unsigned long val)
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{
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}
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#define pl310_set_debug NULL
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#endif
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#ifdef CONFIG_PL310_ERRATA_588369
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static inline void l2x0_flush_line(unsigned long addr)
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{
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void __iomem *base = l2x0_base;
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/* Clean by PA followed by Invalidate by PA */
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cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
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writel_relaxed(addr, base + L2X0_CLEAN_LINE_PA);
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cache_wait(base + L2X0_INV_LINE_PA, 1);
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writel_relaxed(addr, base + L2X0_INV_LINE_PA);
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}
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#else
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static inline void l2x0_flush_line(unsigned long addr)
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{
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void __iomem *base = l2x0_base;
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cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
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writel_relaxed(addr, base + L2X0_CLEAN_INV_LINE_PA);
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}
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#endif
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static void l2x0_cache_sync(void)
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{
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unsigned long flags;
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raw_spin_lock_irqsave(&l2x0_lock, flags);
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cache_sync();
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raw_spin_unlock_irqrestore(&l2x0_lock, flags);
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}
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static void __l2x0_flush_all(void)
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{
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debug_writel(0x03);
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writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_INV_WAY);
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cache_wait_way(l2x0_base + L2X0_CLEAN_INV_WAY, l2x0_way_mask);
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cache_sync();
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debug_writel(0x00);
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}
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static void l2x0_flush_all(void)
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{
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unsigned long flags;
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/* clean all ways */
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raw_spin_lock_irqsave(&l2x0_lock, flags);
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__l2x0_flush_all();
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raw_spin_unlock_irqrestore(&l2x0_lock, flags);
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}
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static void l2x0_clean_all(void)
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{
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unsigned long flags;
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/* clean all ways */
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raw_spin_lock_irqsave(&l2x0_lock, flags);
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writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_WAY);
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cache_wait_way(l2x0_base + L2X0_CLEAN_WAY, l2x0_way_mask);
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cache_sync();
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raw_spin_unlock_irqrestore(&l2x0_lock, flags);
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}
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static void l2x0_inv_all(void)
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{
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unsigned long flags;
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/* invalidate all ways */
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raw_spin_lock_irqsave(&l2x0_lock, flags);
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/* Invalidating when L2 is enabled is a nono */
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BUG_ON(readl(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN);
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writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_INV_WAY);
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cache_wait_way(l2x0_base + L2X0_INV_WAY, l2x0_way_mask);
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cache_sync();
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raw_spin_unlock_irqrestore(&l2x0_lock, flags);
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}
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static void l2x0_inv_range(unsigned long start, unsigned long end)
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{
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void __iomem *base = l2x0_base;
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unsigned long flags;
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raw_spin_lock_irqsave(&l2x0_lock, flags);
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if (start & (CACHE_LINE_SIZE - 1)) {
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start &= ~(CACHE_LINE_SIZE - 1);
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debug_writel(0x03);
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l2x0_flush_line(start);
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debug_writel(0x00);
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start += CACHE_LINE_SIZE;
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}
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if (end & (CACHE_LINE_SIZE - 1)) {
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end &= ~(CACHE_LINE_SIZE - 1);
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debug_writel(0x03);
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l2x0_flush_line(end);
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debug_writel(0x00);
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}
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while (start < end) {
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unsigned long blk_end = start + min(end - start, 4096UL);
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while (start < blk_end) {
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l2x0_inv_line(start);
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start += CACHE_LINE_SIZE;
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}
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if (blk_end < end) {
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raw_spin_unlock_irqrestore(&l2x0_lock, flags);
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raw_spin_lock_irqsave(&l2x0_lock, flags);
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}
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}
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cache_wait(base + L2X0_INV_LINE_PA, 1);
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cache_sync();
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raw_spin_unlock_irqrestore(&l2x0_lock, flags);
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}
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static void l2x0_clean_range(unsigned long start, unsigned long end)
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{
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void __iomem *base = l2x0_base;
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unsigned long flags;
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if ((end - start) >= l2x0_size) {
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l2x0_clean_all();
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return;
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}
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raw_spin_lock_irqsave(&l2x0_lock, flags);
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start &= ~(CACHE_LINE_SIZE - 1);
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while (start < end) {
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unsigned long blk_end = start + min(end - start, 4096UL);
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while (start < blk_end) {
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l2x0_clean_line(start);
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start += CACHE_LINE_SIZE;
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}
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if (blk_end < end) {
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raw_spin_unlock_irqrestore(&l2x0_lock, flags);
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raw_spin_lock_irqsave(&l2x0_lock, flags);
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}
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}
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cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
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cache_sync();
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raw_spin_unlock_irqrestore(&l2x0_lock, flags);
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}
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static void l2x0_flush_range(unsigned long start, unsigned long end)
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{
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void __iomem *base = l2x0_base;
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unsigned long flags;
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if ((end - start) >= l2x0_size) {
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l2x0_flush_all();
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return;
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}
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raw_spin_lock_irqsave(&l2x0_lock, flags);
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start &= ~(CACHE_LINE_SIZE - 1);
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while (start < end) {
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unsigned long blk_end = start + min(end - start, 4096UL);
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debug_writel(0x03);
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while (start < blk_end) {
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l2x0_flush_line(start);
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start += CACHE_LINE_SIZE;
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}
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debug_writel(0x00);
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if (blk_end < end) {
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raw_spin_unlock_irqrestore(&l2x0_lock, flags);
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raw_spin_lock_irqsave(&l2x0_lock, flags);
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}
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}
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cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
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cache_sync();
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raw_spin_unlock_irqrestore(&l2x0_lock, flags);
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}
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static void l2x0_disable(void)
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{
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unsigned long flags;
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raw_spin_lock_irqsave(&l2x0_lock, flags);
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__l2x0_flush_all();
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writel_relaxed(0, l2x0_base + L2X0_CTRL);
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dsb(st);
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raw_spin_unlock_irqrestore(&l2x0_lock, flags);
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}
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static void l2x0_unlock(u32 cache_id)
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{
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int lockregs;
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int i;
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switch (cache_id & L2X0_CACHE_ID_PART_MASK) {
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case L2X0_CACHE_ID_PART_L310:
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lockregs = 8;
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break;
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case AURORA_CACHE_ID:
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lockregs = 4;
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break;
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default:
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/* L210 and unknown types */
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lockregs = 1;
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break;
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}
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for (i = 0; i < lockregs; i++) {
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writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_D_BASE +
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i * L2X0_LOCKDOWN_STRIDE);
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writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_I_BASE +
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i * L2X0_LOCKDOWN_STRIDE);
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}
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}
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void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
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{
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u32 aux;
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u32 cache_id;
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u32 way_size = 0;
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int ways;
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int way_size_shift = L2X0_WAY_SIZE_SHIFT;
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const char *type;
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l2x0_base = base;
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if (cache_id_part_number_from_dt)
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cache_id = cache_id_part_number_from_dt;
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else
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cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID);
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aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
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aux &= aux_mask;
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aux |= aux_val;
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/* Determine the number of ways */
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switch (cache_id & L2X0_CACHE_ID_PART_MASK) {
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case L2X0_CACHE_ID_PART_L310:
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if (aux & (1 << 16))
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ways = 16;
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else
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ways = 8;
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type = "L310";
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#ifdef CONFIG_PL310_ERRATA_753970
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/* Unmapped register. */
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sync_reg_offset = L2X0_DUMMY_REG;
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#endif
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if ((cache_id & L2X0_CACHE_ID_RTL_MASK) <= L2X0_CACHE_ID_RTL_R3P0)
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outer_cache.set_debug = pl310_set_debug;
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break;
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case L2X0_CACHE_ID_PART_L210:
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ways = (aux >> 13) & 0xf;
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type = "L210";
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break;
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case AURORA_CACHE_ID:
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sync_reg_offset = AURORA_SYNC_REG;
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ways = (aux >> 13) & 0xf;
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ways = 2 << ((ways + 1) >> 2);
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way_size_shift = AURORA_WAY_SIZE_SHIFT;
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type = "Aurora";
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break;
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default:
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/* Assume unknown chips have 8 ways */
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ways = 8;
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type = "L2x0 series";
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break;
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}
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l2x0_way_mask = (1 << ways) - 1;
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/*
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* L2 cache Size = Way size * Number of ways
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*/
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way_size = (aux & L2X0_AUX_CTRL_WAY_SIZE_MASK) >> 17;
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way_size = 1 << (way_size + way_size_shift);
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l2x0_size = ways * way_size * SZ_1K;
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/*
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* Check if l2x0 controller is already enabled.
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* If you are booting from non-secure mode
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* accessing the below registers will fault.
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*/
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if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
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/* Make sure that I&D is not locked down when starting */
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l2x0_unlock(cache_id);
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/* l2x0 controller is disabled */
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writel_relaxed(aux, l2x0_base + L2X0_AUX_CTRL);
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l2x0_inv_all();
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/* enable L2X0 */
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writel_relaxed(L2X0_CTRL_EN, l2x0_base + L2X0_CTRL);
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}
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/* Re-read it in case some bits are reserved. */
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aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
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/* Save the value for resuming. */
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l2x0_saved_regs.aux_ctrl = aux;
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if (!of_init) {
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outer_cache.inv_range = l2x0_inv_range;
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outer_cache.clean_range = l2x0_clean_range;
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outer_cache.flush_range = l2x0_flush_range;
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outer_cache.sync = l2x0_cache_sync;
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outer_cache.flush_all = l2x0_flush_all;
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outer_cache.inv_all = l2x0_inv_all;
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outer_cache.disable = l2x0_disable;
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}
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pr_info("%s cache controller enabled\n", type);
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pr_info("l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x, Cache size: %d kB\n",
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ways, cache_id, aux, l2x0_size >> 10);
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}
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#ifdef CONFIG_OF
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static int l2_wt_override;
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/*
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* Note that the end addresses passed to Linux primitives are
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* noninclusive, while the hardware cache range operations use
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* inclusive start and end addresses.
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*/
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static unsigned long calc_range_end(unsigned long start, unsigned long end)
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{
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/*
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* Limit the number of cache lines processed at once,
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* since cache range operations stall the CPU pipeline
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* until completion.
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*/
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if (end > start + MAX_RANGE_SIZE)
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end = start + MAX_RANGE_SIZE;
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/*
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* Cache range operations can't straddle a page boundary.
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*/
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if (end > PAGE_ALIGN(start+1))
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end = PAGE_ALIGN(start+1);
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return end;
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}
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/*
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* Make sure 'start' and 'end' reference the same page, as L2 is PIPT
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* and range operations only do a TLB lookup on the start address.
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*/
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static void aurora_pa_range(unsigned long start, unsigned long end,
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unsigned long offset)
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{
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unsigned long flags;
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raw_spin_lock_irqsave(&l2x0_lock, flags);
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writel_relaxed(start, l2x0_base + AURORA_RANGE_BASE_ADDR_REG);
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writel_relaxed(end, l2x0_base + offset);
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raw_spin_unlock_irqrestore(&l2x0_lock, flags);
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cache_sync();
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}
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static void aurora_inv_range(unsigned long start, unsigned long end)
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{
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/*
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* round start and end adresses up to cache line size
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*/
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start &= ~(CACHE_LINE_SIZE - 1);
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end = ALIGN(end, CACHE_LINE_SIZE);
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/*
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* Invalidate all full cache lines between 'start' and 'end'.
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*/
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while (start < end) {
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unsigned long range_end = calc_range_end(start, end);
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aurora_pa_range(start, range_end - CACHE_LINE_SIZE,
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AURORA_INVAL_RANGE_REG);
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start = range_end;
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}
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}
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static void aurora_clean_range(unsigned long start, unsigned long end)
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{
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/*
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* If L2 is forced to WT, the L2 will always be clean and we
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* don't need to do anything here.
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*/
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if (!l2_wt_override) {
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start &= ~(CACHE_LINE_SIZE - 1);
|
|
end = ALIGN(end, CACHE_LINE_SIZE);
|
|
while (start != end) {
|
|
unsigned long range_end = calc_range_end(start, end);
|
|
aurora_pa_range(start, range_end - CACHE_LINE_SIZE,
|
|
AURORA_CLEAN_RANGE_REG);
|
|
start = range_end;
|
|
}
|
|
}
|
|
}
|
|
|
|
static void aurora_flush_range(unsigned long start, unsigned long end)
|
|
{
|
|
start &= ~(CACHE_LINE_SIZE - 1);
|
|
end = ALIGN(end, CACHE_LINE_SIZE);
|
|
while (start != end) {
|
|
unsigned long range_end = calc_range_end(start, end);
|
|
/*
|
|
* If L2 is forced to WT, the L2 will always be clean and we
|
|
* just need to invalidate.
|
|
*/
|
|
if (l2_wt_override)
|
|
aurora_pa_range(start, range_end - CACHE_LINE_SIZE,
|
|
AURORA_INVAL_RANGE_REG);
|
|
else
|
|
aurora_pa_range(start, range_end - CACHE_LINE_SIZE,
|
|
AURORA_FLUSH_RANGE_REG);
|
|
start = range_end;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* For certain Broadcom SoCs, depending on the address range, different offsets
|
|
* need to be added to the address before passing it to L2 for
|
|
* invalidation/clean/flush
|
|
*
|
|
* Section Address Range Offset EMI
|
|
* 1 0x00000000 - 0x3FFFFFFF 0x80000000 VC
|
|
* 2 0x40000000 - 0xBFFFFFFF 0x40000000 SYS
|
|
* 3 0xC0000000 - 0xFFFFFFFF 0x80000000 VC
|
|
*
|
|
* When the start and end addresses have crossed two different sections, we
|
|
* need to break the L2 operation into two, each within its own section.
|
|
* For example, if we need to invalidate addresses starts at 0xBFFF0000 and
|
|
* ends at 0xC0001000, we need do invalidate 1) 0xBFFF0000 - 0xBFFFFFFF and 2)
|
|
* 0xC0000000 - 0xC0001000
|
|
*
|
|
* Note 1:
|
|
* By breaking a single L2 operation into two, we may potentially suffer some
|
|
* performance hit, but keep in mind the cross section case is very rare
|
|
*
|
|
* Note 2:
|
|
* We do not need to handle the case when the start address is in
|
|
* Section 1 and the end address is in Section 3, since it is not a valid use
|
|
* case
|
|
*
|
|
* Note 3:
|
|
* Section 1 in practical terms can no longer be used on rev A2. Because of
|
|
* that the code does not need to handle section 1 at all.
|
|
*
|
|
*/
|
|
#define BCM_SYS_EMI_START_ADDR 0x40000000UL
|
|
#define BCM_VC_EMI_SEC3_START_ADDR 0xC0000000UL
|
|
|
|
#define BCM_SYS_EMI_OFFSET 0x40000000UL
|
|
#define BCM_VC_EMI_OFFSET 0x80000000UL
|
|
|
|
static inline int bcm_addr_is_sys_emi(unsigned long addr)
|
|
{
|
|
return (addr >= BCM_SYS_EMI_START_ADDR) &&
|
|
(addr < BCM_VC_EMI_SEC3_START_ADDR);
|
|
}
|
|
|
|
static inline unsigned long bcm_l2_phys_addr(unsigned long addr)
|
|
{
|
|
if (bcm_addr_is_sys_emi(addr))
|
|
return addr + BCM_SYS_EMI_OFFSET;
|
|
else
|
|
return addr + BCM_VC_EMI_OFFSET;
|
|
}
|
|
|
|
static void bcm_inv_range(unsigned long start, unsigned long end)
|
|
{
|
|
unsigned long new_start, new_end;
|
|
|
|
BUG_ON(start < BCM_SYS_EMI_START_ADDR);
|
|
|
|
if (unlikely(end <= start))
|
|
return;
|
|
|
|
new_start = bcm_l2_phys_addr(start);
|
|
new_end = bcm_l2_phys_addr(end);
|
|
|
|
/* normal case, no cross section between start and end */
|
|
if (likely(bcm_addr_is_sys_emi(end) || !bcm_addr_is_sys_emi(start))) {
|
|
l2x0_inv_range(new_start, new_end);
|
|
return;
|
|
}
|
|
|
|
/* They cross sections, so it can only be a cross from section
|
|
* 2 to section 3
|
|
*/
|
|
l2x0_inv_range(new_start,
|
|
bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR-1));
|
|
l2x0_inv_range(bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR),
|
|
new_end);
|
|
}
|
|
|
|
static void bcm_clean_range(unsigned long start, unsigned long end)
|
|
{
|
|
unsigned long new_start, new_end;
|
|
|
|
BUG_ON(start < BCM_SYS_EMI_START_ADDR);
|
|
|
|
if (unlikely(end <= start))
|
|
return;
|
|
|
|
if ((end - start) >= l2x0_size) {
|
|
l2x0_clean_all();
|
|
return;
|
|
}
|
|
|
|
new_start = bcm_l2_phys_addr(start);
|
|
new_end = bcm_l2_phys_addr(end);
|
|
|
|
/* normal case, no cross section between start and end */
|
|
if (likely(bcm_addr_is_sys_emi(end) || !bcm_addr_is_sys_emi(start))) {
|
|
l2x0_clean_range(new_start, new_end);
|
|
return;
|
|
}
|
|
|
|
/* They cross sections, so it can only be a cross from section
|
|
* 2 to section 3
|
|
*/
|
|
l2x0_clean_range(new_start,
|
|
bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR-1));
|
|
l2x0_clean_range(bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR),
|
|
new_end);
|
|
}
|
|
|
|
static void bcm_flush_range(unsigned long start, unsigned long end)
|
|
{
|
|
unsigned long new_start, new_end;
|
|
|
|
BUG_ON(start < BCM_SYS_EMI_START_ADDR);
|
|
|
|
if (unlikely(end <= start))
|
|
return;
|
|
|
|
if ((end - start) >= l2x0_size) {
|
|
l2x0_flush_all();
|
|
return;
|
|
}
|
|
|
|
new_start = bcm_l2_phys_addr(start);
|
|
new_end = bcm_l2_phys_addr(end);
|
|
|
|
/* normal case, no cross section between start and end */
|
|
if (likely(bcm_addr_is_sys_emi(end) || !bcm_addr_is_sys_emi(start))) {
|
|
l2x0_flush_range(new_start, new_end);
|
|
return;
|
|
}
|
|
|
|
/* They cross sections, so it can only be a cross from section
|
|
* 2 to section 3
|
|
*/
|
|
l2x0_flush_range(new_start,
|
|
bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR-1));
|
|
l2x0_flush_range(bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR),
|
|
new_end);
|
|
}
|
|
|
|
static void __init l2x0_of_setup(const struct device_node *np,
|
|
u32 *aux_val, u32 *aux_mask)
|
|
{
|
|
u32 data[2] = { 0, 0 };
|
|
u32 tag = 0;
|
|
u32 dirty = 0;
|
|
u32 val = 0, mask = 0;
|
|
|
|
of_property_read_u32(np, "arm,tag-latency", &tag);
|
|
if (tag) {
|
|
mask |= L2X0_AUX_CTRL_TAG_LATENCY_MASK;
|
|
val |= (tag - 1) << L2X0_AUX_CTRL_TAG_LATENCY_SHIFT;
|
|
}
|
|
|
|
of_property_read_u32_array(np, "arm,data-latency",
|
|
data, ARRAY_SIZE(data));
|
|
if (data[0] && data[1]) {
|
|
mask |= L2X0_AUX_CTRL_DATA_RD_LATENCY_MASK |
|
|
L2X0_AUX_CTRL_DATA_WR_LATENCY_MASK;
|
|
val |= ((data[0] - 1) << L2X0_AUX_CTRL_DATA_RD_LATENCY_SHIFT) |
|
|
((data[1] - 1) << L2X0_AUX_CTRL_DATA_WR_LATENCY_SHIFT);
|
|
}
|
|
|
|
of_property_read_u32(np, "arm,dirty-latency", &dirty);
|
|
if (dirty) {
|
|
mask |= L2X0_AUX_CTRL_DIRTY_LATENCY_MASK;
|
|
val |= (dirty - 1) << L2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT;
|
|
}
|
|
|
|
*aux_val &= ~mask;
|
|
*aux_val |= val;
|
|
*aux_mask &= ~mask;
|
|
}
|
|
|
|
static void __init pl310_of_setup(const struct device_node *np,
|
|
u32 *aux_val, u32 *aux_mask)
|
|
{
|
|
u32 data[3] = { 0, 0, 0 };
|
|
u32 tag[3] = { 0, 0, 0 };
|
|
u32 filter[2] = { 0, 0 };
|
|
|
|
of_property_read_u32_array(np, "arm,tag-latency", tag, ARRAY_SIZE(tag));
|
|
if (tag[0] && tag[1] && tag[2])
|
|
writel_relaxed(
|
|
((tag[0] - 1) << L2X0_LATENCY_CTRL_RD_SHIFT) |
|
|
((tag[1] - 1) << L2X0_LATENCY_CTRL_WR_SHIFT) |
|
|
((tag[2] - 1) << L2X0_LATENCY_CTRL_SETUP_SHIFT),
|
|
l2x0_base + L2X0_TAG_LATENCY_CTRL);
|
|
|
|
of_property_read_u32_array(np, "arm,data-latency",
|
|
data, ARRAY_SIZE(data));
|
|
if (data[0] && data[1] && data[2])
|
|
writel_relaxed(
|
|
((data[0] - 1) << L2X0_LATENCY_CTRL_RD_SHIFT) |
|
|
((data[1] - 1) << L2X0_LATENCY_CTRL_WR_SHIFT) |
|
|
((data[2] - 1) << L2X0_LATENCY_CTRL_SETUP_SHIFT),
|
|
l2x0_base + L2X0_DATA_LATENCY_CTRL);
|
|
|
|
of_property_read_u32_array(np, "arm,filter-ranges",
|
|
filter, ARRAY_SIZE(filter));
|
|
if (filter[1]) {
|
|
writel_relaxed(ALIGN(filter[0] + filter[1], SZ_1M),
|
|
l2x0_base + L2X0_ADDR_FILTER_END);
|
|
writel_relaxed((filter[0] & ~(SZ_1M - 1)) | L2X0_ADDR_FILTER_EN,
|
|
l2x0_base + L2X0_ADDR_FILTER_START);
|
|
}
|
|
}
|
|
|
|
static void __init pl310_save(void)
|
|
{
|
|
u32 l2x0_revision = readl_relaxed(l2x0_base + L2X0_CACHE_ID) &
|
|
L2X0_CACHE_ID_RTL_MASK;
|
|
|
|
l2x0_saved_regs.tag_latency = readl_relaxed(l2x0_base +
|
|
L2X0_TAG_LATENCY_CTRL);
|
|
l2x0_saved_regs.data_latency = readl_relaxed(l2x0_base +
|
|
L2X0_DATA_LATENCY_CTRL);
|
|
l2x0_saved_regs.filter_end = readl_relaxed(l2x0_base +
|
|
L2X0_ADDR_FILTER_END);
|
|
l2x0_saved_regs.filter_start = readl_relaxed(l2x0_base +
|
|
L2X0_ADDR_FILTER_START);
|
|
|
|
if (l2x0_revision >= L2X0_CACHE_ID_RTL_R2P0) {
|
|
/*
|
|
* From r2p0, there is Prefetch offset/control register
|
|
*/
|
|
l2x0_saved_regs.prefetch_ctrl = readl_relaxed(l2x0_base +
|
|
L2X0_PREFETCH_CTRL);
|
|
/*
|
|
* From r3p0, there is Power control register
|
|
*/
|
|
if (l2x0_revision >= L2X0_CACHE_ID_RTL_R3P0)
|
|
l2x0_saved_regs.pwr_ctrl = readl_relaxed(l2x0_base +
|
|
L2X0_POWER_CTRL);
|
|
}
|
|
}
|
|
|
|
static void aurora_save(void)
|
|
{
|
|
l2x0_saved_regs.ctrl = readl_relaxed(l2x0_base + L2X0_CTRL);
|
|
l2x0_saved_regs.aux_ctrl = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
|
|
}
|
|
|
|
static void l2x0_resume(void)
|
|
{
|
|
if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
|
|
/* restore aux ctrl and enable l2 */
|
|
l2x0_unlock(readl_relaxed(l2x0_base + L2X0_CACHE_ID));
|
|
|
|
writel_relaxed(l2x0_saved_regs.aux_ctrl, l2x0_base +
|
|
L2X0_AUX_CTRL);
|
|
|
|
l2x0_inv_all();
|
|
|
|
writel_relaxed(L2X0_CTRL_EN, l2x0_base + L2X0_CTRL);
|
|
}
|
|
}
|
|
|
|
static void pl310_resume(void)
|
|
{
|
|
u32 l2x0_revision;
|
|
|
|
if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
|
|
/* restore pl310 setup */
|
|
writel_relaxed(l2x0_saved_regs.tag_latency,
|
|
l2x0_base + L2X0_TAG_LATENCY_CTRL);
|
|
writel_relaxed(l2x0_saved_regs.data_latency,
|
|
l2x0_base + L2X0_DATA_LATENCY_CTRL);
|
|
writel_relaxed(l2x0_saved_regs.filter_end,
|
|
l2x0_base + L2X0_ADDR_FILTER_END);
|
|
writel_relaxed(l2x0_saved_regs.filter_start,
|
|
l2x0_base + L2X0_ADDR_FILTER_START);
|
|
|
|
l2x0_revision = readl_relaxed(l2x0_base + L2X0_CACHE_ID) &
|
|
L2X0_CACHE_ID_RTL_MASK;
|
|
|
|
if (l2x0_revision >= L2X0_CACHE_ID_RTL_R2P0) {
|
|
writel_relaxed(l2x0_saved_regs.prefetch_ctrl,
|
|
l2x0_base + L2X0_PREFETCH_CTRL);
|
|
if (l2x0_revision >= L2X0_CACHE_ID_RTL_R3P0)
|
|
writel_relaxed(l2x0_saved_regs.pwr_ctrl,
|
|
l2x0_base + L2X0_POWER_CTRL);
|
|
}
|
|
}
|
|
|
|
l2x0_resume();
|
|
}
|
|
|
|
static void aurora_resume(void)
|
|
{
|
|
if (!(readl(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
|
|
writel_relaxed(l2x0_saved_regs.aux_ctrl,
|
|
l2x0_base + L2X0_AUX_CTRL);
|
|
writel_relaxed(l2x0_saved_regs.ctrl, l2x0_base + L2X0_CTRL);
|
|
}
|
|
}
|
|
|
|
static void __init aurora_broadcast_l2_commands(void)
|
|
{
|
|
__u32 u;
|
|
/* Enable Broadcasting of cache commands to L2*/
|
|
__asm__ __volatile__("mrc p15, 1, %0, c15, c2, 0" : "=r"(u));
|
|
u |= AURORA_CTRL_FW; /* Set the FW bit */
|
|
__asm__ __volatile__("mcr p15, 1, %0, c15, c2, 0\n" : : "r"(u));
|
|
isb();
|
|
}
|
|
|
|
static void __init aurora_of_setup(const struct device_node *np,
|
|
u32 *aux_val, u32 *aux_mask)
|
|
{
|
|
u32 val = AURORA_ACR_REPLACEMENT_TYPE_SEMIPLRU;
|
|
u32 mask = AURORA_ACR_REPLACEMENT_MASK;
|
|
|
|
of_property_read_u32(np, "cache-id-part",
|
|
&cache_id_part_number_from_dt);
|
|
|
|
/* Determine and save the write policy */
|
|
l2_wt_override = of_property_read_bool(np, "wt-override");
|
|
|
|
if (l2_wt_override) {
|
|
val |= AURORA_ACR_FORCE_WRITE_THRO_POLICY;
|
|
mask |= AURORA_ACR_FORCE_WRITE_POLICY_MASK;
|
|
}
|
|
|
|
*aux_val &= ~mask;
|
|
*aux_val |= val;
|
|
*aux_mask &= ~mask;
|
|
}
|
|
|
|
static const struct l2x0_of_data pl310_data = {
|
|
.setup = pl310_of_setup,
|
|
.save = pl310_save,
|
|
.outer_cache = {
|
|
.resume = pl310_resume,
|
|
.inv_range = l2x0_inv_range,
|
|
.clean_range = l2x0_clean_range,
|
|
.flush_range = l2x0_flush_range,
|
|
.sync = l2x0_cache_sync,
|
|
.flush_all = l2x0_flush_all,
|
|
.inv_all = l2x0_inv_all,
|
|
.disable = l2x0_disable,
|
|
},
|
|
};
|
|
|
|
static const struct l2x0_of_data l2x0_data = {
|
|
.setup = l2x0_of_setup,
|
|
.save = NULL,
|
|
.outer_cache = {
|
|
.resume = l2x0_resume,
|
|
.inv_range = l2x0_inv_range,
|
|
.clean_range = l2x0_clean_range,
|
|
.flush_range = l2x0_flush_range,
|
|
.sync = l2x0_cache_sync,
|
|
.flush_all = l2x0_flush_all,
|
|
.inv_all = l2x0_inv_all,
|
|
.disable = l2x0_disable,
|
|
},
|
|
};
|
|
|
|
static const struct l2x0_of_data aurora_with_outer_data = {
|
|
.setup = aurora_of_setup,
|
|
.save = aurora_save,
|
|
.outer_cache = {
|
|
.resume = aurora_resume,
|
|
.inv_range = aurora_inv_range,
|
|
.clean_range = aurora_clean_range,
|
|
.flush_range = aurora_flush_range,
|
|
.sync = l2x0_cache_sync,
|
|
.flush_all = l2x0_flush_all,
|
|
.inv_all = l2x0_inv_all,
|
|
.disable = l2x0_disable,
|
|
},
|
|
};
|
|
|
|
static const struct l2x0_of_data aurora_no_outer_data = {
|
|
.setup = aurora_of_setup,
|
|
.save = aurora_save,
|
|
.outer_cache = {
|
|
.resume = aurora_resume,
|
|
},
|
|
};
|
|
|
|
static const struct l2x0_of_data bcm_l2x0_data = {
|
|
.setup = pl310_of_setup,
|
|
.save = pl310_save,
|
|
.outer_cache = {
|
|
.resume = pl310_resume,
|
|
.inv_range = bcm_inv_range,
|
|
.clean_range = bcm_clean_range,
|
|
.flush_range = bcm_flush_range,
|
|
.sync = l2x0_cache_sync,
|
|
.flush_all = l2x0_flush_all,
|
|
.inv_all = l2x0_inv_all,
|
|
.disable = l2x0_disable,
|
|
},
|
|
};
|
|
|
|
static const struct of_device_id l2x0_ids[] __initconst = {
|
|
{ .compatible = "arm,pl310-cache", .data = (void *)&pl310_data },
|
|
{ .compatible = "arm,l220-cache", .data = (void *)&l2x0_data },
|
|
{ .compatible = "arm,l210-cache", .data = (void *)&l2x0_data },
|
|
{ .compatible = "marvell,aurora-system-cache",
|
|
.data = (void *)&aurora_no_outer_data},
|
|
{ .compatible = "marvell,aurora-outer-cache",
|
|
.data = (void *)&aurora_with_outer_data},
|
|
{ .compatible = "brcm,bcm11351-a2-pl310-cache",
|
|
.data = (void *)&bcm_l2x0_data},
|
|
{ .compatible = "bcm,bcm11351-a2-pl310-cache", /* deprecated name */
|
|
.data = (void *)&bcm_l2x0_data},
|
|
{}
|
|
};
|
|
|
|
int __init l2x0_of_init(u32 aux_val, u32 aux_mask)
|
|
{
|
|
struct device_node *np;
|
|
const struct l2x0_of_data *data;
|
|
struct resource res;
|
|
|
|
np = of_find_matching_node(NULL, l2x0_ids);
|
|
if (!np)
|
|
return -ENODEV;
|
|
|
|
if (of_address_to_resource(np, 0, &res))
|
|
return -ENODEV;
|
|
|
|
l2x0_base = ioremap(res.start, resource_size(&res));
|
|
if (!l2x0_base)
|
|
return -ENOMEM;
|
|
|
|
l2x0_saved_regs.phy_base = res.start;
|
|
|
|
data = of_match_node(l2x0_ids, np)->data;
|
|
|
|
/* L2 configuration can only be changed if the cache is disabled */
|
|
if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
|
|
if (data->setup)
|
|
data->setup(np, &aux_val, &aux_mask);
|
|
|
|
/* For aurora cache in no outer mode select the
|
|
* correct mode using the coprocessor*/
|
|
if (data == &aurora_no_outer_data)
|
|
aurora_broadcast_l2_commands();
|
|
}
|
|
|
|
if (data->save)
|
|
data->save();
|
|
|
|
of_init = true;
|
|
memcpy(&outer_cache, &data->outer_cache, sizeof(outer_cache));
|
|
l2x0_init(l2x0_base, aux_val, aux_mask);
|
|
|
|
return 0;
|
|
}
|
|
#endif
|