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4947793916
In pcie_isr(), we return early if no status bits other than
PCI_EXP_SLTSTA_CC are set. This was introduced by dbd79aed1a
("pciehp:
fix NULL dereference in interrupt handler"), but it is no longer necessary
because all the subsequent pcie_isr() code is already predicated on a
status bit being set.
Remove the unnecessary test for ~PCI_EXP_SLTSTA_CC. No functional change
intended.
Tested-by: Lukas Wunner <lukas@wunner.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
863 lines
23 KiB
C
863 lines
23 KiB
C
/*
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* PCI Express PCI Hot Plug Driver
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*
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* Copyright (C) 1995,2001 Compaq Computer Corporation
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* Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
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* Copyright (C) 2001 IBM Corp.
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* Copyright (C) 2003-2004 Intel Corporation
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*
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* All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or (at
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* your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for more
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* details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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* Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
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*
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/signal.h>
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#include <linux/jiffies.h>
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#include <linux/timer.h>
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#include <linux/pci.h>
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#include <linux/interrupt.h>
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#include <linux/time.h>
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#include <linux/slab.h>
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#include "../pci.h"
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#include "pciehp.h"
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static inline struct pci_dev *ctrl_dev(struct controller *ctrl)
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{
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return ctrl->pcie->port;
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}
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static irqreturn_t pcie_isr(int irq, void *dev_id);
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static void start_int_poll_timer(struct controller *ctrl, int sec);
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/* This is the interrupt polling timeout function. */
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static void int_poll_timeout(unsigned long data)
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{
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struct controller *ctrl = (struct controller *)data;
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/* Poll for interrupt events. regs == NULL => polling */
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pcie_isr(0, ctrl);
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init_timer(&ctrl->poll_timer);
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if (!pciehp_poll_time)
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pciehp_poll_time = 2; /* default polling interval is 2 sec */
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start_int_poll_timer(ctrl, pciehp_poll_time);
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}
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/* This function starts the interrupt polling timer. */
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static void start_int_poll_timer(struct controller *ctrl, int sec)
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{
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/* Clamp to sane value */
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if ((sec <= 0) || (sec > 60))
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sec = 2;
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ctrl->poll_timer.function = &int_poll_timeout;
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ctrl->poll_timer.data = (unsigned long)ctrl;
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ctrl->poll_timer.expires = jiffies + sec * HZ;
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add_timer(&ctrl->poll_timer);
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}
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static inline int pciehp_request_irq(struct controller *ctrl)
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{
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int retval, irq = ctrl->pcie->irq;
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/* Install interrupt polling timer. Start with 10 sec delay */
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if (pciehp_poll_mode) {
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init_timer(&ctrl->poll_timer);
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start_int_poll_timer(ctrl, 10);
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return 0;
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}
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/* Installs the interrupt handler */
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retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl);
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if (retval)
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ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n",
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irq);
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return retval;
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}
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static inline void pciehp_free_irq(struct controller *ctrl)
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{
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if (pciehp_poll_mode)
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del_timer_sync(&ctrl->poll_timer);
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else
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free_irq(ctrl->pcie->irq, ctrl);
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}
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static int pcie_poll_cmd(struct controller *ctrl, int timeout)
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{
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struct pci_dev *pdev = ctrl_dev(ctrl);
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u16 slot_status;
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while (true) {
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pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
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if (slot_status == (u16) ~0) {
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ctrl_info(ctrl, "%s: no response from device\n",
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__func__);
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return 0;
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}
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if (slot_status & PCI_EXP_SLTSTA_CC) {
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pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
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PCI_EXP_SLTSTA_CC);
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return 1;
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}
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if (timeout < 0)
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break;
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msleep(10);
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timeout -= 10;
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}
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return 0; /* timeout */
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}
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static void pcie_wait_cmd(struct controller *ctrl)
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{
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unsigned int msecs = pciehp_poll_mode ? 2500 : 1000;
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unsigned long duration = msecs_to_jiffies(msecs);
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unsigned long cmd_timeout = ctrl->cmd_started + duration;
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unsigned long now, timeout;
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int rc;
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/*
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* If the controller does not generate notifications for command
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* completions, we never need to wait between writes.
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*/
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if (NO_CMD_CMPL(ctrl))
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return;
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if (!ctrl->cmd_busy)
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return;
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/*
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* Even if the command has already timed out, we want to call
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* pcie_poll_cmd() so it can clear PCI_EXP_SLTSTA_CC.
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*/
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now = jiffies;
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if (time_before_eq(cmd_timeout, now))
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timeout = 1;
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else
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timeout = cmd_timeout - now;
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if (ctrl->slot_ctrl & PCI_EXP_SLTCTL_HPIE &&
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ctrl->slot_ctrl & PCI_EXP_SLTCTL_CCIE)
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rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout);
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else
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rc = pcie_poll_cmd(ctrl, jiffies_to_msecs(timeout));
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/*
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* Controllers with errata like Intel CF118 don't generate
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* completion notifications unless the power/indicator/interlock
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* control bits are changed. On such controllers, we'll emit this
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* timeout message when we wait for completion of commands that
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* don't change those bits, e.g., commands that merely enable
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* interrupts.
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*/
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if (!rc)
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ctrl_info(ctrl, "Timeout on hotplug command %#06x (issued %u msec ago)\n",
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ctrl->slot_ctrl,
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jiffies_to_msecs(jiffies - ctrl->cmd_started));
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}
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static void pcie_do_write_cmd(struct controller *ctrl, u16 cmd,
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u16 mask, bool wait)
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{
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struct pci_dev *pdev = ctrl_dev(ctrl);
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u16 slot_ctrl;
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mutex_lock(&ctrl->ctrl_lock);
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/*
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* Always wait for any previous command that might still be in progress
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*/
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pcie_wait_cmd(ctrl);
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pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
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if (slot_ctrl == (u16) ~0) {
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ctrl_info(ctrl, "%s: no response from device\n", __func__);
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goto out;
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}
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slot_ctrl &= ~mask;
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slot_ctrl |= (cmd & mask);
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ctrl->cmd_busy = 1;
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smp_mb();
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pcie_capability_write_word(pdev, PCI_EXP_SLTCTL, slot_ctrl);
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ctrl->cmd_started = jiffies;
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ctrl->slot_ctrl = slot_ctrl;
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/*
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* Optionally wait for the hardware to be ready for a new command,
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* indicating completion of the above issued command.
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*/
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if (wait)
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pcie_wait_cmd(ctrl);
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out:
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mutex_unlock(&ctrl->ctrl_lock);
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}
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/**
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* pcie_write_cmd - Issue controller command
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* @ctrl: controller to which the command is issued
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* @cmd: command value written to slot control register
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* @mask: bitmask of slot control register to be modified
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*/
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static void pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask)
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{
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pcie_do_write_cmd(ctrl, cmd, mask, true);
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}
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/* Same as above without waiting for the hardware to latch */
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static void pcie_write_cmd_nowait(struct controller *ctrl, u16 cmd, u16 mask)
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{
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pcie_do_write_cmd(ctrl, cmd, mask, false);
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}
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bool pciehp_check_link_active(struct controller *ctrl)
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{
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struct pci_dev *pdev = ctrl_dev(ctrl);
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u16 lnk_status;
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bool ret;
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pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
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ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA);
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if (ret)
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ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
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return ret;
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}
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static void __pcie_wait_link_active(struct controller *ctrl, bool active)
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{
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int timeout = 1000;
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if (pciehp_check_link_active(ctrl) == active)
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return;
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while (timeout > 0) {
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msleep(10);
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timeout -= 10;
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if (pciehp_check_link_active(ctrl) == active)
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return;
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}
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ctrl_dbg(ctrl, "Data Link Layer Link Active not %s in 1000 msec\n",
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active ? "set" : "cleared");
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}
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static void pcie_wait_link_active(struct controller *ctrl)
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{
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__pcie_wait_link_active(ctrl, true);
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}
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static bool pci_bus_check_dev(struct pci_bus *bus, int devfn)
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{
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u32 l;
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int count = 0;
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int delay = 1000, step = 20;
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bool found = false;
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do {
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found = pci_bus_read_dev_vendor_id(bus, devfn, &l, 0);
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count++;
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if (found)
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break;
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msleep(step);
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delay -= step;
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} while (delay > 0);
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if (count > 1 && pciehp_debug)
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printk(KERN_DEBUG "pci %04x:%02x:%02x.%d id reading try %d times with interval %d ms to get %08x\n",
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pci_domain_nr(bus), bus->number, PCI_SLOT(devfn),
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PCI_FUNC(devfn), count, step, l);
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return found;
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}
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int pciehp_check_link_status(struct controller *ctrl)
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{
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struct pci_dev *pdev = ctrl_dev(ctrl);
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bool found;
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u16 lnk_status;
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/*
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* Data Link Layer Link Active Reporting must be capable for
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* hot-plug capable downstream port. But old controller might
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* not implement it. In this case, we wait for 1000 ms.
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*/
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if (ctrl->link_active_reporting)
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pcie_wait_link_active(ctrl);
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else
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msleep(1000);
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/* wait 100ms before read pci conf, and try in 1s */
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msleep(100);
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found = pci_bus_check_dev(ctrl->pcie->port->subordinate,
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PCI_DEVFN(0, 0));
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pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
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ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
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if ((lnk_status & PCI_EXP_LNKSTA_LT) ||
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!(lnk_status & PCI_EXP_LNKSTA_NLW)) {
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ctrl_err(ctrl, "link training error: status %#06x\n",
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lnk_status);
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return -1;
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}
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pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status);
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if (!found)
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return -1;
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return 0;
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}
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static int __pciehp_link_set(struct controller *ctrl, bool enable)
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{
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struct pci_dev *pdev = ctrl_dev(ctrl);
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u16 lnk_ctrl;
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pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &lnk_ctrl);
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if (enable)
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lnk_ctrl &= ~PCI_EXP_LNKCTL_LD;
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else
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lnk_ctrl |= PCI_EXP_LNKCTL_LD;
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pcie_capability_write_word(pdev, PCI_EXP_LNKCTL, lnk_ctrl);
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ctrl_dbg(ctrl, "%s: lnk_ctrl = %x\n", __func__, lnk_ctrl);
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return 0;
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}
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static int pciehp_link_enable(struct controller *ctrl)
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{
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return __pciehp_link_set(ctrl, true);
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}
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void pciehp_get_attention_status(struct slot *slot, u8 *status)
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{
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struct controller *ctrl = slot->ctrl;
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struct pci_dev *pdev = ctrl_dev(ctrl);
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u16 slot_ctrl;
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pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
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ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", __func__,
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pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
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switch (slot_ctrl & PCI_EXP_SLTCTL_AIC) {
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case PCI_EXP_SLTCTL_ATTN_IND_ON:
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*status = 1; /* On */
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break;
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case PCI_EXP_SLTCTL_ATTN_IND_BLINK:
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*status = 2; /* Blink */
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break;
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case PCI_EXP_SLTCTL_ATTN_IND_OFF:
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*status = 0; /* Off */
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break;
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default:
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*status = 0xFF;
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break;
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}
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}
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void pciehp_get_power_status(struct slot *slot, u8 *status)
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{
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struct controller *ctrl = slot->ctrl;
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struct pci_dev *pdev = ctrl_dev(ctrl);
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u16 slot_ctrl;
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pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
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ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", __func__,
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pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
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switch (slot_ctrl & PCI_EXP_SLTCTL_PCC) {
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case PCI_EXP_SLTCTL_PWR_ON:
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*status = 1; /* On */
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break;
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case PCI_EXP_SLTCTL_PWR_OFF:
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*status = 0; /* Off */
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break;
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default:
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*status = 0xFF;
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break;
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}
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}
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void pciehp_get_latch_status(struct slot *slot, u8 *status)
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{
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struct pci_dev *pdev = ctrl_dev(slot->ctrl);
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u16 slot_status;
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pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
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*status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS);
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}
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void pciehp_get_adapter_status(struct slot *slot, u8 *status)
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{
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struct pci_dev *pdev = ctrl_dev(slot->ctrl);
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u16 slot_status;
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pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
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*status = !!(slot_status & PCI_EXP_SLTSTA_PDS);
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}
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int pciehp_query_power_fault(struct slot *slot)
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{
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struct pci_dev *pdev = ctrl_dev(slot->ctrl);
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u16 slot_status;
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pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
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return !!(slot_status & PCI_EXP_SLTSTA_PFD);
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}
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void pciehp_set_attention_status(struct slot *slot, u8 value)
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{
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struct controller *ctrl = slot->ctrl;
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u16 slot_cmd;
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if (!ATTN_LED(ctrl))
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return;
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switch (value) {
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case 0: /* turn off */
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slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_OFF;
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break;
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case 1: /* turn on */
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slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_ON;
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break;
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case 2: /* turn blink */
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slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_BLINK;
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break;
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default:
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return;
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}
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pcie_write_cmd_nowait(ctrl, slot_cmd, PCI_EXP_SLTCTL_AIC);
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ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
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pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
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}
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void pciehp_green_led_on(struct slot *slot)
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{
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struct controller *ctrl = slot->ctrl;
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if (!PWR_LED(ctrl))
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return;
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pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_PWR_IND_ON,
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PCI_EXP_SLTCTL_PIC);
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ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
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pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
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PCI_EXP_SLTCTL_PWR_IND_ON);
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}
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void pciehp_green_led_off(struct slot *slot)
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{
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struct controller *ctrl = slot->ctrl;
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if (!PWR_LED(ctrl))
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return;
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pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_PWR_IND_OFF,
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PCI_EXP_SLTCTL_PIC);
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ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
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pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
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PCI_EXP_SLTCTL_PWR_IND_OFF);
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}
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void pciehp_green_led_blink(struct slot *slot)
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{
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struct controller *ctrl = slot->ctrl;
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if (!PWR_LED(ctrl))
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return;
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pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_PWR_IND_BLINK,
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PCI_EXP_SLTCTL_PIC);
|
|
ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
|
|
pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
|
|
PCI_EXP_SLTCTL_PWR_IND_BLINK);
|
|
}
|
|
|
|
int pciehp_power_on_slot(struct slot *slot)
|
|
{
|
|
struct controller *ctrl = slot->ctrl;
|
|
struct pci_dev *pdev = ctrl_dev(ctrl);
|
|
u16 slot_status;
|
|
int retval;
|
|
|
|
/* Clear sticky power-fault bit from previous power failures */
|
|
pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
|
|
if (slot_status & PCI_EXP_SLTSTA_PFD)
|
|
pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
|
|
PCI_EXP_SLTSTA_PFD);
|
|
ctrl->power_fault_detected = 0;
|
|
|
|
pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_ON, PCI_EXP_SLTCTL_PCC);
|
|
ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
|
|
pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
|
|
PCI_EXP_SLTCTL_PWR_ON);
|
|
|
|
retval = pciehp_link_enable(ctrl);
|
|
if (retval)
|
|
ctrl_err(ctrl, "%s: Can not enable the link!\n", __func__);
|
|
|
|
return retval;
|
|
}
|
|
|
|
void pciehp_power_off_slot(struct slot *slot)
|
|
{
|
|
struct controller *ctrl = slot->ctrl;
|
|
|
|
pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_OFF, PCI_EXP_SLTCTL_PCC);
|
|
ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
|
|
pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
|
|
PCI_EXP_SLTCTL_PWR_OFF);
|
|
}
|
|
|
|
static irqreturn_t pciehp_isr(int irq, void *dev_id)
|
|
{
|
|
struct controller *ctrl = (struct controller *)dev_id;
|
|
struct pci_dev *pdev = ctrl_dev(ctrl);
|
|
struct pci_bus *subordinate = pdev->subordinate;
|
|
struct pci_dev *dev;
|
|
struct slot *slot = ctrl->slot;
|
|
u16 status, events;
|
|
u8 present;
|
|
bool link;
|
|
|
|
/* Interrupts cannot originate from a controller that's asleep */
|
|
if (pdev->current_state == PCI_D3cold)
|
|
return IRQ_NONE;
|
|
|
|
pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &status);
|
|
if (status == (u16) ~0) {
|
|
ctrl_info(ctrl, "%s: no response from device\n", __func__);
|
|
return IRQ_NONE;
|
|
}
|
|
|
|
/*
|
|
* Slot Status contains plain status bits as well as event
|
|
* notification bits; right now we only want the event bits.
|
|
*/
|
|
events = status & (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
|
|
PCI_EXP_SLTSTA_PDC | PCI_EXP_SLTSTA_CC |
|
|
PCI_EXP_SLTSTA_DLLSC);
|
|
if (!events)
|
|
return IRQ_NONE;
|
|
|
|
/* Capture link status before clearing interrupts */
|
|
if (events & PCI_EXP_SLTSTA_DLLSC)
|
|
link = pciehp_check_link_active(ctrl);
|
|
|
|
pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, events);
|
|
ctrl_dbg(ctrl, "pending interrupts %#06x from Slot Status\n", events);
|
|
|
|
/* Check Command Complete Interrupt Pending */
|
|
if (events & PCI_EXP_SLTSTA_CC) {
|
|
ctrl->cmd_busy = 0;
|
|
smp_mb();
|
|
wake_up(&ctrl->queue);
|
|
}
|
|
|
|
if (subordinate) {
|
|
list_for_each_entry(dev, &subordinate->devices, bus_list) {
|
|
if (dev->ignore_hotplug) {
|
|
ctrl_dbg(ctrl, "ignoring hotplug event %#06x (%s requested no hotplug)\n",
|
|
events, pci_name(dev));
|
|
return IRQ_HANDLED;
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Check Attention Button Pressed */
|
|
if (events & PCI_EXP_SLTSTA_ABP) {
|
|
ctrl_info(ctrl, "Button pressed on Slot(%s)\n",
|
|
slot_name(slot));
|
|
pciehp_queue_interrupt_event(slot, INT_BUTTON_PRESS);
|
|
}
|
|
|
|
/* Check Presence Detect Changed */
|
|
if (events & PCI_EXP_SLTSTA_PDC) {
|
|
present = !!(status & PCI_EXP_SLTSTA_PDS);
|
|
ctrl_info(ctrl, "Card %spresent on Slot(%s)\n",
|
|
present ? "" : "not ", slot_name(slot));
|
|
pciehp_queue_interrupt_event(slot, present ? INT_PRESENCE_ON :
|
|
INT_PRESENCE_OFF);
|
|
}
|
|
|
|
/* Check Power Fault Detected */
|
|
if ((events & PCI_EXP_SLTSTA_PFD) && !ctrl->power_fault_detected) {
|
|
ctrl->power_fault_detected = 1;
|
|
ctrl_err(ctrl, "Power fault on slot %s\n", slot_name(slot));
|
|
pciehp_queue_interrupt_event(slot, INT_POWER_FAULT);
|
|
}
|
|
|
|
if (events & PCI_EXP_SLTSTA_DLLSC) {
|
|
ctrl_info(ctrl, "slot(%s): Link %s event\n",
|
|
slot_name(slot), link ? "Up" : "Down");
|
|
pciehp_queue_interrupt_event(slot, link ? INT_LINK_UP :
|
|
INT_LINK_DOWN);
|
|
}
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static irqreturn_t pcie_isr(int irq, void *dev_id)
|
|
{
|
|
irqreturn_t rc, handled = IRQ_NONE;
|
|
|
|
/*
|
|
* To guarantee that all interrupt events are serviced, we need to
|
|
* re-inspect Slot Status register after clearing what is presumed
|
|
* to be the last pending interrupt.
|
|
*/
|
|
do {
|
|
rc = pciehp_isr(irq, dev_id);
|
|
if (rc == IRQ_HANDLED)
|
|
handled = IRQ_HANDLED;
|
|
} while (rc == IRQ_HANDLED);
|
|
|
|
/* Return IRQ_HANDLED if we handled one or more events */
|
|
return handled;
|
|
}
|
|
|
|
void pcie_enable_notification(struct controller *ctrl)
|
|
{
|
|
u16 cmd, mask;
|
|
|
|
/*
|
|
* TBD: Power fault detected software notification support.
|
|
*
|
|
* Power fault detected software notification is not enabled
|
|
* now, because it caused power fault detected interrupt storm
|
|
* on some machines. On those machines, power fault detected
|
|
* bit in the slot status register was set again immediately
|
|
* when it is cleared in the interrupt service routine, and
|
|
* next power fault detected interrupt was notified again.
|
|
*/
|
|
|
|
/*
|
|
* Always enable link events: thus link-up and link-down shall
|
|
* always be treated as hotplug and unplug respectively. Enable
|
|
* presence detect only if Attention Button is not present.
|
|
*/
|
|
cmd = PCI_EXP_SLTCTL_DLLSCE;
|
|
if (ATTN_BUTTN(ctrl))
|
|
cmd |= PCI_EXP_SLTCTL_ABPE;
|
|
else
|
|
cmd |= PCI_EXP_SLTCTL_PDCE;
|
|
if (!pciehp_poll_mode)
|
|
cmd |= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE;
|
|
|
|
mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
|
|
PCI_EXP_SLTCTL_PFDE |
|
|
PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE |
|
|
PCI_EXP_SLTCTL_DLLSCE);
|
|
|
|
pcie_write_cmd_nowait(ctrl, cmd, mask);
|
|
ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
|
|
pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, cmd);
|
|
}
|
|
|
|
static void pcie_disable_notification(struct controller *ctrl)
|
|
{
|
|
u16 mask;
|
|
|
|
mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
|
|
PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
|
|
PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE |
|
|
PCI_EXP_SLTCTL_DLLSCE);
|
|
pcie_write_cmd(ctrl, 0, mask);
|
|
ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
|
|
pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0);
|
|
}
|
|
|
|
/*
|
|
* pciehp has a 1:1 bus:slot relationship so we ultimately want a secondary
|
|
* bus reset of the bridge, but at the same time we want to ensure that it is
|
|
* not seen as a hot-unplug, followed by the hot-plug of the device. Thus,
|
|
* disable link state notification and presence detection change notification
|
|
* momentarily, if we see that they could interfere. Also, clear any spurious
|
|
* events after.
|
|
*/
|
|
int pciehp_reset_slot(struct slot *slot, int probe)
|
|
{
|
|
struct controller *ctrl = slot->ctrl;
|
|
struct pci_dev *pdev = ctrl_dev(ctrl);
|
|
u16 stat_mask = 0, ctrl_mask = 0;
|
|
|
|
if (probe)
|
|
return 0;
|
|
|
|
if (!ATTN_BUTTN(ctrl)) {
|
|
ctrl_mask |= PCI_EXP_SLTCTL_PDCE;
|
|
stat_mask |= PCI_EXP_SLTSTA_PDC;
|
|
}
|
|
ctrl_mask |= PCI_EXP_SLTCTL_DLLSCE;
|
|
stat_mask |= PCI_EXP_SLTSTA_DLLSC;
|
|
|
|
pcie_write_cmd(ctrl, 0, ctrl_mask);
|
|
ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
|
|
pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0);
|
|
if (pciehp_poll_mode)
|
|
del_timer_sync(&ctrl->poll_timer);
|
|
|
|
pci_reset_bridge_secondary_bus(ctrl->pcie->port);
|
|
|
|
pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, stat_mask);
|
|
pcie_write_cmd_nowait(ctrl, ctrl_mask, ctrl_mask);
|
|
ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
|
|
pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, ctrl_mask);
|
|
if (pciehp_poll_mode)
|
|
int_poll_timeout(ctrl->poll_timer.data);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int pcie_init_notification(struct controller *ctrl)
|
|
{
|
|
if (pciehp_request_irq(ctrl))
|
|
return -1;
|
|
pcie_enable_notification(ctrl);
|
|
ctrl->notification_enabled = 1;
|
|
return 0;
|
|
}
|
|
|
|
static void pcie_shutdown_notification(struct controller *ctrl)
|
|
{
|
|
if (ctrl->notification_enabled) {
|
|
pcie_disable_notification(ctrl);
|
|
pciehp_free_irq(ctrl);
|
|
ctrl->notification_enabled = 0;
|
|
}
|
|
}
|
|
|
|
static int pcie_init_slot(struct controller *ctrl)
|
|
{
|
|
struct slot *slot;
|
|
|
|
slot = kzalloc(sizeof(*slot), GFP_KERNEL);
|
|
if (!slot)
|
|
return -ENOMEM;
|
|
|
|
slot->wq = alloc_workqueue("pciehp-%u", 0, 0, PSN(ctrl));
|
|
if (!slot->wq)
|
|
goto abort;
|
|
|
|
slot->ctrl = ctrl;
|
|
mutex_init(&slot->lock);
|
|
mutex_init(&slot->hotplug_lock);
|
|
INIT_DELAYED_WORK(&slot->work, pciehp_queue_pushbutton_work);
|
|
ctrl->slot = slot;
|
|
return 0;
|
|
abort:
|
|
kfree(slot);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
static void pcie_cleanup_slot(struct controller *ctrl)
|
|
{
|
|
struct slot *slot = ctrl->slot;
|
|
cancel_delayed_work(&slot->work);
|
|
destroy_workqueue(slot->wq);
|
|
kfree(slot);
|
|
}
|
|
|
|
static inline void dbg_ctrl(struct controller *ctrl)
|
|
{
|
|
struct pci_dev *pdev = ctrl->pcie->port;
|
|
u16 reg16;
|
|
|
|
if (!pciehp_debug)
|
|
return;
|
|
|
|
ctrl_info(ctrl, "Slot Capabilities : 0x%08x\n", ctrl->slot_cap);
|
|
pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, ®16);
|
|
ctrl_info(ctrl, "Slot Status : 0x%04x\n", reg16);
|
|
pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, ®16);
|
|
ctrl_info(ctrl, "Slot Control : 0x%04x\n", reg16);
|
|
}
|
|
|
|
#define FLAG(x, y) (((x) & (y)) ? '+' : '-')
|
|
|
|
struct controller *pcie_init(struct pcie_device *dev)
|
|
{
|
|
struct controller *ctrl;
|
|
u32 slot_cap, link_cap;
|
|
struct pci_dev *pdev = dev->port;
|
|
|
|
ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
|
|
if (!ctrl) {
|
|
dev_err(&dev->device, "%s: Out of memory\n", __func__);
|
|
goto abort;
|
|
}
|
|
ctrl->pcie = dev;
|
|
pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &slot_cap);
|
|
ctrl->slot_cap = slot_cap;
|
|
mutex_init(&ctrl->ctrl_lock);
|
|
init_waitqueue_head(&ctrl->queue);
|
|
dbg_ctrl(ctrl);
|
|
|
|
/* Check if Data Link Layer Link Active Reporting is implemented */
|
|
pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, &link_cap);
|
|
if (link_cap & PCI_EXP_LNKCAP_DLLLARC)
|
|
ctrl->link_active_reporting = 1;
|
|
|
|
/* Clear all remaining event bits in Slot Status register */
|
|
pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
|
|
PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
|
|
PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC |
|
|
PCI_EXP_SLTSTA_CC | PCI_EXP_SLTSTA_DLLSC);
|
|
|
|
ctrl_info(ctrl, "Slot #%d AttnBtn%c PwrCtrl%c MRL%c AttnInd%c PwrInd%c HotPlug%c Surprise%c Interlock%c NoCompl%c LLActRep%c\n",
|
|
(slot_cap & PCI_EXP_SLTCAP_PSN) >> 19,
|
|
FLAG(slot_cap, PCI_EXP_SLTCAP_ABP),
|
|
FLAG(slot_cap, PCI_EXP_SLTCAP_PCP),
|
|
FLAG(slot_cap, PCI_EXP_SLTCAP_MRLSP),
|
|
FLAG(slot_cap, PCI_EXP_SLTCAP_AIP),
|
|
FLAG(slot_cap, PCI_EXP_SLTCAP_PIP),
|
|
FLAG(slot_cap, PCI_EXP_SLTCAP_HPC),
|
|
FLAG(slot_cap, PCI_EXP_SLTCAP_HPS),
|
|
FLAG(slot_cap, PCI_EXP_SLTCAP_EIP),
|
|
FLAG(slot_cap, PCI_EXP_SLTCAP_NCCS),
|
|
FLAG(link_cap, PCI_EXP_LNKCAP_DLLLARC));
|
|
|
|
if (pcie_init_slot(ctrl))
|
|
goto abort_ctrl;
|
|
|
|
return ctrl;
|
|
|
|
abort_ctrl:
|
|
kfree(ctrl);
|
|
abort:
|
|
return NULL;
|
|
}
|
|
|
|
void pciehp_release_ctrl(struct controller *ctrl)
|
|
{
|
|
pcie_shutdown_notification(ctrl);
|
|
pcie_cleanup_slot(ctrl);
|
|
kfree(ctrl);
|
|
}
|