Michel Thierry 48ea1e32c3 drm/i915/gen9: Set PIN_ZONE_4G end to 4GB - 1 page ... Kernel and userspace are able to handle 4GB (1<<32) address space range, but "A32 Stateless Model" is not. According to documentation, A32 accesses are based on General State Base Address and bound checking is in place. Because size field (instruction State Base Address) limitation, it is not possible to address full 4GB memory region. A32 Stateless Model is used by some libraries and without this patch, the last page of 4GB address space is not accessible in 32bit processes. Reported-by: Artur Harasimiuk <artur.harasimiuk@intel.com> Signed-off-by: Michel Thierry <michel.thierry@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1452512367-23614-1-git-send-email-michel.thierry@intel.com Cc: drm-intel-fixes@lists.freedesktop.org Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> (cherry picked from commit 1892faa9ec) Signed-off-by: Jani Nikula <jani.nikula@intel.com>		2016-01-13 10:50:55 +02:00
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drm	drm/i915/gen9: Set PIN_ZONE_4G end to 4GB - 1 page	2016-01-13 10:50:55 +02:00
host1x	gpu: host1x: Fix MLOCK's debug info	2015-10-02 14:40:12 +02:00
ipu-v3	gpu: ipu-v3: Assign of_node of child platform devices to corresponding ports	2015-11-24 11:30:17 +01:00
vga	vga_switcheroo: Drop client power state VGA_SWITCHEROO_INIT	2015-11-05 11:07:36 +10:00
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