mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-28 07:04:00 +08:00
69e0b57a91
This adds dpm support for cayman asics. This includes: - clockgating - dynamic engine clock scaling - dynamic memory clock scaling - dynamic voltage scaling - dynamic pcie gen1/gen2 switching (requires additional acpi support) - power containment - shader power scaling Set radeon.dpm=1 to enable. v2: fold in tdp fix v3: fix indentation v4: fix 64 bit div v5: attempt to fix state enable Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jerome Glisse <jglisse@redhat.com>
330 lines
11 KiB
C
330 lines
11 KiB
C
/*
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* Copyright 2012 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __NISLANDS_SMC_H__
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#define __NISLANDS_SMC_H__
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#pragma pack(push, 1)
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#define NISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE 16
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struct PP_NIslands_Dpm2PerfLevel
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{
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uint8_t MaxPS;
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uint8_t TgtAct;
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uint8_t MaxPS_StepInc;
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uint8_t MaxPS_StepDec;
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uint8_t PSST;
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uint8_t NearTDPDec;
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uint8_t AboveSafeInc;
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uint8_t BelowSafeInc;
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uint8_t PSDeltaLimit;
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uint8_t PSDeltaWin;
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uint8_t Reserved[6];
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};
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typedef struct PP_NIslands_Dpm2PerfLevel PP_NIslands_Dpm2PerfLevel;
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struct PP_NIslands_DPM2Parameters
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{
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uint32_t TDPLimit;
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uint32_t NearTDPLimit;
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uint32_t SafePowerLimit;
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uint32_t PowerBoostLimit;
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};
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typedef struct PP_NIslands_DPM2Parameters PP_NIslands_DPM2Parameters;
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struct NISLANDS_SMC_SCLK_VALUE
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{
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uint32_t vCG_SPLL_FUNC_CNTL;
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uint32_t vCG_SPLL_FUNC_CNTL_2;
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uint32_t vCG_SPLL_FUNC_CNTL_3;
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uint32_t vCG_SPLL_FUNC_CNTL_4;
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uint32_t vCG_SPLL_SPREAD_SPECTRUM;
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uint32_t vCG_SPLL_SPREAD_SPECTRUM_2;
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uint32_t sclk_value;
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};
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typedef struct NISLANDS_SMC_SCLK_VALUE NISLANDS_SMC_SCLK_VALUE;
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struct NISLANDS_SMC_MCLK_VALUE
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{
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uint32_t vMPLL_FUNC_CNTL;
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uint32_t vMPLL_FUNC_CNTL_1;
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uint32_t vMPLL_FUNC_CNTL_2;
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uint32_t vMPLL_AD_FUNC_CNTL;
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uint32_t vMPLL_AD_FUNC_CNTL_2;
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uint32_t vMPLL_DQ_FUNC_CNTL;
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uint32_t vMPLL_DQ_FUNC_CNTL_2;
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uint32_t vMCLK_PWRMGT_CNTL;
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uint32_t vDLL_CNTL;
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uint32_t vMPLL_SS;
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uint32_t vMPLL_SS2;
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uint32_t mclk_value;
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};
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typedef struct NISLANDS_SMC_MCLK_VALUE NISLANDS_SMC_MCLK_VALUE;
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struct NISLANDS_SMC_VOLTAGE_VALUE
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{
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uint16_t value;
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uint8_t index;
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uint8_t padding;
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};
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typedef struct NISLANDS_SMC_VOLTAGE_VALUE NISLANDS_SMC_VOLTAGE_VALUE;
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struct NISLANDS_SMC_HW_PERFORMANCE_LEVEL
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{
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uint8_t arbValue;
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uint8_t ACIndex;
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uint8_t displayWatermark;
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uint8_t gen2PCIE;
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uint8_t reserved1;
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uint8_t reserved2;
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uint8_t strobeMode;
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uint8_t mcFlags;
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uint32_t aT;
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uint32_t bSP;
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NISLANDS_SMC_SCLK_VALUE sclk;
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NISLANDS_SMC_MCLK_VALUE mclk;
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NISLANDS_SMC_VOLTAGE_VALUE vddc;
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NISLANDS_SMC_VOLTAGE_VALUE mvdd;
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NISLANDS_SMC_VOLTAGE_VALUE vddci;
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NISLANDS_SMC_VOLTAGE_VALUE std_vddc;
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uint32_t powergate_en;
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uint8_t hUp;
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uint8_t hDown;
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uint8_t stateFlags;
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uint8_t arbRefreshState;
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uint32_t SQPowerThrottle;
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uint32_t SQPowerThrottle_2;
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uint32_t reserved[2];
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PP_NIslands_Dpm2PerfLevel dpm2;
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};
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#define NISLANDS_SMC_STROBE_RATIO 0x0F
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#define NISLANDS_SMC_STROBE_ENABLE 0x10
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#define NISLANDS_SMC_MC_EDC_RD_FLAG 0x01
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#define NISLANDS_SMC_MC_EDC_WR_FLAG 0x02
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#define NISLANDS_SMC_MC_RTT_ENABLE 0x04
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#define NISLANDS_SMC_MC_STUTTER_EN 0x08
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typedef struct NISLANDS_SMC_HW_PERFORMANCE_LEVEL NISLANDS_SMC_HW_PERFORMANCE_LEVEL;
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struct NISLANDS_SMC_SWSTATE
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{
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uint8_t flags;
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uint8_t levelCount;
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uint8_t padding2;
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uint8_t padding3;
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NISLANDS_SMC_HW_PERFORMANCE_LEVEL levels[1];
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};
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typedef struct NISLANDS_SMC_SWSTATE NISLANDS_SMC_SWSTATE;
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#define NISLANDS_SMC_VOLTAGEMASK_VDDC 0
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#define NISLANDS_SMC_VOLTAGEMASK_MVDD 1
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#define NISLANDS_SMC_VOLTAGEMASK_VDDCI 2
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#define NISLANDS_SMC_VOLTAGEMASK_MAX 4
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struct NISLANDS_SMC_VOLTAGEMASKTABLE
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{
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uint8_t highMask[NISLANDS_SMC_VOLTAGEMASK_MAX];
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uint32_t lowMask[NISLANDS_SMC_VOLTAGEMASK_MAX];
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};
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typedef struct NISLANDS_SMC_VOLTAGEMASKTABLE NISLANDS_SMC_VOLTAGEMASKTABLE;
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#define NISLANDS_MAX_NO_VREG_STEPS 32
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struct NISLANDS_SMC_STATETABLE
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{
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uint8_t thermalProtectType;
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uint8_t systemFlags;
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uint8_t maxVDDCIndexInPPTable;
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uint8_t extraFlags;
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uint8_t highSMIO[NISLANDS_MAX_NO_VREG_STEPS];
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uint32_t lowSMIO[NISLANDS_MAX_NO_VREG_STEPS];
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NISLANDS_SMC_VOLTAGEMASKTABLE voltageMaskTable;
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PP_NIslands_DPM2Parameters dpm2Params;
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NISLANDS_SMC_SWSTATE initialState;
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NISLANDS_SMC_SWSTATE ACPIState;
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NISLANDS_SMC_SWSTATE ULVState;
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NISLANDS_SMC_SWSTATE driverState;
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NISLANDS_SMC_HW_PERFORMANCE_LEVEL dpmLevels[NISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE - 1];
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};
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typedef struct NISLANDS_SMC_STATETABLE NISLANDS_SMC_STATETABLE;
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#define NI_SMC_SOFT_REGISTERS_START 0x108
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#define NI_SMC_SOFT_REGISTER_mclk_chg_timeout 0x0
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#define NI_SMC_SOFT_REGISTER_delay_bbias 0xC
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#define NI_SMC_SOFT_REGISTER_delay_vreg 0x10
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#define NI_SMC_SOFT_REGISTER_delay_acpi 0x2C
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#define NI_SMC_SOFT_REGISTER_seq_index 0x64
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#define NI_SMC_SOFT_REGISTER_mvdd_chg_time 0x68
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#define NI_SMC_SOFT_REGISTER_mclk_switch_lim 0x78
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#define NI_SMC_SOFT_REGISTER_watermark_threshold 0x80
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#define NI_SMC_SOFT_REGISTER_mc_block_delay 0x84
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#define NI_SMC_SOFT_REGISTER_uvd_enabled 0x98
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#define SMC_NISLANDS_MC_TPP_CAC_NUM_OF_ENTRIES 16
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#define SMC_NISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES 16
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#define SMC_NISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES 16
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#define SMC_NISLANDS_BIF_LUT_NUM_OF_ENTRIES 4
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struct SMC_NISLANDS_MC_TPP_CAC_TABLE
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{
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uint32_t tpp[SMC_NISLANDS_MC_TPP_CAC_NUM_OF_ENTRIES];
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uint32_t cacValue[SMC_NISLANDS_MC_TPP_CAC_NUM_OF_ENTRIES];
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};
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typedef struct SMC_NISLANDS_MC_TPP_CAC_TABLE SMC_NISLANDS_MC_TPP_CAC_TABLE;
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struct PP_NIslands_CACTABLES
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{
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uint32_t cac_bif_lut[SMC_NISLANDS_BIF_LUT_NUM_OF_ENTRIES];
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uint32_t cac_lkge_lut[SMC_NISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES][SMC_NISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES];
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uint32_t pwr_const;
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uint32_t dc_cacValue;
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uint32_t bif_cacValue;
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uint32_t lkge_pwr;
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uint8_t cac_width;
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uint8_t window_size_p2;
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uint8_t num_drop_lsb;
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uint8_t padding_0;
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uint32_t last_power;
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uint8_t AllowOvrflw;
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uint8_t MCWrWeight;
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uint8_t MCRdWeight;
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uint8_t padding_1[9];
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uint8_t enableWinAvg;
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uint8_t numWin_TDP;
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uint8_t l2numWin_TDP;
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uint8_t WinIndex;
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uint32_t dynPwr_TDP[4];
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uint32_t lkgePwr_TDP[4];
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uint32_t power_TDP[4];
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uint32_t avg_dynPwr_TDP;
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uint32_t avg_lkgePwr_TDP;
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uint32_t avg_power_TDP;
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uint32_t lts_power_TDP;
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uint8_t lts_truncate_n;
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uint8_t padding_2[7];
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};
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typedef struct PP_NIslands_CACTABLES PP_NIslands_CACTABLES;
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#define SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE 32
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#define SMC_NISLANDS_MC_REGISTER_ARRAY_SET_COUNT 20
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struct SMC_NIslands_MCRegisterAddress
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{
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uint16_t s0;
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uint16_t s1;
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};
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typedef struct SMC_NIslands_MCRegisterAddress SMC_NIslands_MCRegisterAddress;
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struct SMC_NIslands_MCRegisterSet
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{
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uint32_t value[SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE];
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};
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typedef struct SMC_NIslands_MCRegisterSet SMC_NIslands_MCRegisterSet;
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struct SMC_NIslands_MCRegisters
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{
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uint8_t last;
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uint8_t reserved[3];
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SMC_NIslands_MCRegisterAddress address[SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE];
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SMC_NIslands_MCRegisterSet data[SMC_NISLANDS_MC_REGISTER_ARRAY_SET_COUNT];
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};
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typedef struct SMC_NIslands_MCRegisters SMC_NIslands_MCRegisters;
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struct SMC_NIslands_MCArbDramTimingRegisterSet
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{
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uint32_t mc_arb_dram_timing;
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uint32_t mc_arb_dram_timing2;
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uint8_t mc_arb_rfsh_rate;
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uint8_t padding[3];
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};
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typedef struct SMC_NIslands_MCArbDramTimingRegisterSet SMC_NIslands_MCArbDramTimingRegisterSet;
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struct SMC_NIslands_MCArbDramTimingRegisters
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{
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uint8_t arb_current;
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uint8_t reserved[3];
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SMC_NIslands_MCArbDramTimingRegisterSet data[20];
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};
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typedef struct SMC_NIslands_MCArbDramTimingRegisters SMC_NIslands_MCArbDramTimingRegisters;
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struct SMC_NISLANDS_SPLL_DIV_TABLE
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{
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uint32_t freq[256];
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uint32_t ss[256];
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};
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#define SMC_NISLANDS_SPLL_DIV_TABLE_FBDIV_MASK 0x01ffffff
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#define SMC_NISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT 0
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#define SMC_NISLANDS_SPLL_DIV_TABLE_PDIV_MASK 0xfe000000
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#define SMC_NISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT 25
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#define SMC_NISLANDS_SPLL_DIV_TABLE_CLKV_MASK 0x000fffff
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#define SMC_NISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT 0
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#define SMC_NISLANDS_SPLL_DIV_TABLE_CLKS_MASK 0xfff00000
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#define SMC_NISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT 20
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typedef struct SMC_NISLANDS_SPLL_DIV_TABLE SMC_NISLANDS_SPLL_DIV_TABLE;
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#define NISLANDS_SMC_FIRMWARE_HEADER_LOCATION 0x100
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#define NISLANDS_SMC_FIRMWARE_HEADER_version 0x0
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#define NISLANDS_SMC_FIRMWARE_HEADER_flags 0x4
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#define NISLANDS_SMC_FIRMWARE_HEADER_softRegisters 0x8
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#define NISLANDS_SMC_FIRMWARE_HEADER_stateTable 0xC
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#define NISLANDS_SMC_FIRMWARE_HEADER_fanTable 0x10
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#define NISLANDS_SMC_FIRMWARE_HEADER_cacTable 0x14
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#define NISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable 0x20
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#define NISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable 0x2C
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#define NISLANDS_SMC_FIRMWARE_HEADER_spllTable 0x30
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#pragma pack(pop)
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#endif
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