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48269c78fb
The TLB only matches the ASID when the global bit isn't set, so dump_tlb() shouldn't really be skipping global entries just because the ASID doesn't match. Fix the condition to read the TLB entry's global bit from EntryLo0. Note that after a TLB read the global bits in both EntryLo registers reflect the same global bit in the TLB entry. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10079/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
122 lines
3.1 KiB
C
122 lines
3.1 KiB
C
/*
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* Dump R4x00 TLB for debugging purposes.
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*
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* Copyright (C) 1994, 1995 by Waldorf Electronics, written by Ralf Baechle.
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* Copyright (C) 1999 by Silicon Graphics, Inc.
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*/
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <asm/hazards.h>
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#include <asm/mipsregs.h>
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#include <asm/page.h>
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#include <asm/pgtable.h>
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#include <asm/tlbdebug.h>
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static inline const char *msk2str(unsigned int mask)
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{
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switch (mask) {
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case PM_4K: return "4kb";
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case PM_16K: return "16kb";
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case PM_64K: return "64kb";
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case PM_256K: return "256kb";
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#ifdef CONFIG_CPU_CAVIUM_OCTEON
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case PM_8K: return "8kb";
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case PM_32K: return "32kb";
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case PM_128K: return "128kb";
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case PM_512K: return "512kb";
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case PM_2M: return "2Mb";
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case PM_8M: return "8Mb";
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case PM_32M: return "32Mb";
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#endif
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#ifndef CONFIG_CPU_VR41XX
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case PM_1M: return "1Mb";
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case PM_4M: return "4Mb";
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case PM_16M: return "16Mb";
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case PM_64M: return "64Mb";
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case PM_256M: return "256Mb";
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case PM_1G: return "1Gb";
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#endif
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}
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return "";
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}
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static void dump_tlb(int first, int last)
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{
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unsigned long s_entryhi, entryhi, asid;
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unsigned long long entrylo0, entrylo1;
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unsigned int s_index, s_pagemask, pagemask, c0, c1, i;
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#ifdef CONFIG_32BIT
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int width = 8;
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#else
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int width = 11;
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#endif
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s_pagemask = read_c0_pagemask();
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s_entryhi = read_c0_entryhi();
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s_index = read_c0_index();
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asid = s_entryhi & 0xff;
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for (i = first; i <= last; i++) {
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write_c0_index(i);
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mtc0_tlbr_hazard();
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tlb_read();
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tlb_read_hazard();
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pagemask = read_c0_pagemask();
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entryhi = read_c0_entryhi();
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entrylo0 = read_c0_entrylo0();
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entrylo1 = read_c0_entrylo1();
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/*
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* Prior to tlbinv, unused entries have a virtual address of
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* CKSEG0.
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*/
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if ((entryhi & ~0x1ffffUL) == CKSEG0)
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continue;
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/*
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* ASID takes effect in absence of G (global) bit.
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* We check both G bits, even though architecturally they should
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* match one another, because some revisions of the SB1 core may
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* leave only a single G bit set after a machine check exception
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* due to duplicate TLB entry.
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*/
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if (!((entrylo0 | entrylo1) & MIPS_ENTRYLO_G) &&
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(entryhi & 0xff) != asid)
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continue;
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/*
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* Only print entries in use
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*/
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printk("Index: %2d pgmask=%s ", i, msk2str(pagemask));
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c0 = (entrylo0 & MIPS_ENTRYLO_C) >> MIPS_ENTRYLO_C_SHIFT;
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c1 = (entrylo1 & MIPS_ENTRYLO_C) >> MIPS_ENTRYLO_C_SHIFT;
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printk("va=%0*lx asid=%02lx\n",
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width, (entryhi & ~0x1fffUL),
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entryhi & 0xff);
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printk("\t[pa=%0*llx c=%d d=%d v=%d g=%d] ",
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width,
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(entrylo0 << 6) & PAGE_MASK, c0,
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(entrylo0 & MIPS_ENTRYLO_D) ? 1 : 0,
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(entrylo0 & MIPS_ENTRYLO_V) ? 1 : 0,
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(entrylo0 & MIPS_ENTRYLO_G) ? 1 : 0);
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printk("[pa=%0*llx c=%d d=%d v=%d g=%d]\n",
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width,
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(entrylo1 << 6) & PAGE_MASK, c1,
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(entrylo1 & MIPS_ENTRYLO_D) ? 1 : 0,
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(entrylo1 & MIPS_ENTRYLO_V) ? 1 : 0,
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(entrylo1 & MIPS_ENTRYLO_G) ? 1 : 0);
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}
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printk("\n");
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write_c0_entryhi(s_entryhi);
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write_c0_index(s_index);
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write_c0_pagemask(s_pagemask);
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}
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void dump_tlb_all(void)
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{
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dump_tlb(0, current_cpu_data.tlbsize - 1);
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}
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