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88dde5e23d
While the clocks are fairly similar to the H6, many differ in tiny details, so a separate clock driver seems indicated. Derived from the H6 clock driver, and adjusted according to the manual. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20210127172500.13356-4-andre.przywara@arm.com
57 lines
1.2 KiB
C
57 lines
1.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright 2020 Arm Ltd.
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*/
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#ifndef _CCU_SUN50I_H616_H_
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#define _CCU_SUN50I_H616_H_
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#include <dt-bindings/clock/sun50i-h616-ccu.h>
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#include <dt-bindings/reset/sun50i-h616-ccu.h>
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#define CLK_OSC12M 0
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#define CLK_PLL_CPUX 1
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#define CLK_PLL_DDR0 2
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#define CLK_PLL_DDR1 3
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/* PLL_PERIPH0 exported for PRCM */
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#define CLK_PLL_PERIPH0_2X 5
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#define CLK_PLL_PERIPH1 6
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#define CLK_PLL_PERIPH1_2X 7
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#define CLK_PLL_GPU 8
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#define CLK_PLL_VIDEO0 9
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#define CLK_PLL_VIDEO0_4X 10
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#define CLK_PLL_VIDEO1 11
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#define CLK_PLL_VIDEO1_4X 12
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#define CLK_PLL_VIDEO2 13
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#define CLK_PLL_VIDEO2_4X 14
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#define CLK_PLL_VE 15
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#define CLK_PLL_DE 16
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#define CLK_PLL_AUDIO_HS 17
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#define CLK_PLL_AUDIO_1X 18
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#define CLK_PLL_AUDIO_2X 19
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#define CLK_PLL_AUDIO_4X 20
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/* CPUX clock exported for DVFS */
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#define CLK_AXI 22
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#define CLK_CPUX_APB 23
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#define CLK_PSI_AHB1_AHB2 24
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#define CLK_AHB3 25
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/* APB1 clock exported for PIO */
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#define CLK_APB2 27
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#define CLK_MBUS 28
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/* All module clocks and bus gates are exported except DRAM */
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#define CLK_DRAM 49
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#define CLK_BUS_DRAM 56
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#define CLK_NUMBER (CLK_BUS_HDCP + 1)
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#endif /* _CCU_SUN50I_H616_H_ */
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