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4df64c3e58
Current device tree is only bare bones. This patch adds nodes to make
it a complete tree for the MPC5121ads.
Added nodes include:
mbx - opengl coprocessor
nfc - nand flash controller
cpld-pic - on board cpld
rtc
clock - clock control
pmc - power management control
gpio
mscan - can module
i2c
axe - audio coprocessor
display - display interface unit
mdio
ethernet
usb
ioctl - pin config
pata
ac97 - PSC configured as AC97
pscfifo - psc fifo configuration
dma
pci
Fix typo in header changing MDS to ADS.
Add a compatible property of the form "fsl,mpc5121-..."
to nodes missing one.
Changed localbus compatible to fsl,mpc5121-localbus, this does
not break anything because the only code that uses it finds it
via the node name, not compatible.
Signed-off-by: John Rigby <jrigby@freescale.com>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
411 lines
9.4 KiB
Plaintext
411 lines
9.4 KiB
Plaintext
/*
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* MPC5121E ADS Device Tree Source
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*
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* Copyright 2007,2008 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/dts-v1/;
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/ {
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model = "mpc5121ads";
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compatible = "fsl,mpc5121ads";
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#address-cells = <1>;
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#size-cells = <1>;
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aliases {
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pci = &pci;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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PowerPC,5121@0 {
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device_type = "cpu";
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reg = <0>;
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d-cache-line-size = <0x20>; // 32 bytes
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i-cache-line-size = <0x20>; // 32 bytes
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d-cache-size = <0x8000>; // L1, 32K
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i-cache-size = <0x8000>; // L1, 32K
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timebase-frequency = <49500000>;// 49.5 MHz (csb/4)
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bus-frequency = <198000000>; // 198 MHz csb bus
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clock-frequency = <396000000>; // 396 MHz ppc core
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};
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};
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memory {
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device_type = "memory";
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reg = <0x00000000 0x10000000>; // 256MB at 0
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};
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mbx@20000000 {
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compatible = "fsl,mpc5121-mbx";
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reg = <0x20000000 0x4000>;
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interrupts = <66 0x8>;
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interrupt-parent = < &ipic >;
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};
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sram@30000000 {
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compatible = "fsl,mpc5121-sram";
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reg = <0x30000000 0x20000>; // 128K at 0x30000000
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};
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nfc@40000000 {
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compatible = "fsl,mpc5121-nfc";
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reg = <0x40000000 0x100000>; // 1M at 0x40000000
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interrupts = <6 8>;
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interrupt-parent = < &ipic >;
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#address-cells = <1>;
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#size-cells = <1>;
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bank-width = <1>;
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// ADS has two Hynix 512MB Nand flash chips in a single
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// stacked package .
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chips = <2>;
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nand0@0 {
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label = "nand0";
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reg = <0x00000000 0x02000000>; // first 32 MB of chip 0
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};
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nand1@20000000 {
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label = "nand1";
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reg = <0x20000000 0x02000000>; // first 32 MB of chip 1
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};
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};
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localbus@80000020 {
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compatible = "fsl,mpc5121-localbus";
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#address-cells = <2>;
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#size-cells = <1>;
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reg = <0x80000020 0x40>;
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ranges = <0x0 0x0 0xfc000000 0x04000000
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0x2 0x0 0x82000000 0x00008000>;
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flash@0,0 {
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compatible = "cfi-flash";
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reg = <0 0x0 0x4000000>;
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#address-cells = <1>;
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#size-cells = <1>;
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bank-width = <4>;
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device-width = <2>;
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protected@0 {
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label = "protected";
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reg = <0x00000000 0x00040000>; // first sector is protected
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read-only;
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};
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filesystem@40000 {
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label = "filesystem";
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reg = <0x00040000 0x03c00000>; // 60M for filesystem
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};
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kernel@3c40000 {
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label = "kernel";
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reg = <0x03c40000 0x00280000>; // 2.5M for kernel
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};
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device-tree@3ec0000 {
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label = "device-tree";
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reg = <0x03ec0000 0x00040000>; // one sector for device tree
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};
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u-boot@3f00000 {
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label = "u-boot";
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reg = <0x03f00000 0x00100000>; // 1M for u-boot
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read-only;
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};
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};
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board-control@2,0 {
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compatible = "fsl,mpc5121ads-cpld";
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reg = <0x2 0x0 0x8000>;
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};
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cpld_pic: pic@2,a {
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compatible = "fsl,mpc5121ads-cpld-pic";
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x2 0xa 0x5>;
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interrupt-parent = < &ipic >;
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// irq routing
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// all irqs but touch screen are routed to irq0 (ipic 48)
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// touch screen is statically routed to irq1 (ipic 17)
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// so don't use it here
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interrupts = <48 0x8>;
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};
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};
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soc@80000000 {
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compatible = "fsl,mpc5121-immr";
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#address-cells = <1>;
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#size-cells = <1>;
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#interrupt-cells = <2>;
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ranges = <0x0 0x80000000 0x400000>;
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reg = <0x80000000 0x400000>;
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bus-frequency = <66000000>; // 66 MHz ips bus
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// IPIC
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// interrupts cell = <intr #, sense>
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// sense values match linux IORESOURCE_IRQ_* defines:
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// sense == 8: Level, low assertion
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// sense == 2: Edge, high-to-low change
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//
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ipic: interrupt-controller@c00 {
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compatible = "fsl,mpc5121-ipic", "fsl,ipic";
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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reg = <0xc00 0x100>;
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};
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rtc@a00 { // Real time clock
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compatible = "fsl,mpc5121-rtc";
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reg = <0xa00 0x100>;
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interrupts = <79 0x8 80 0x8>;
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interrupt-parent = < &ipic >;
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};
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clock@f00 { // Clock control
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compatible = "fsl,mpc5121-clock";
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reg = <0xf00 0x100>;
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};
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pmc@1000{ //Power Management Controller
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compatible = "fsl,mpc5121-pmc";
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reg = <0x1000 0x100>;
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interrupts = <83 0x2>;
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interrupt-parent = < &ipic >;
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};
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gpio@1100 {
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compatible = "fsl,mpc5121-gpio";
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reg = <0x1100 0x100>;
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interrupts = <78 0x8>;
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interrupt-parent = < &ipic >;
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};
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mscan@1300 {
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compatible = "fsl,mpc5121-mscan";
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cell-index = <0>;
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interrupts = <12 0x8>;
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interrupt-parent = < &ipic >;
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reg = <0x1300 0x80>;
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};
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mscan@1380 {
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compatible = "fsl,mpc5121-mscan";
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cell-index = <1>;
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interrupts = <13 0x8>;
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interrupt-parent = < &ipic >;
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reg = <0x1380 0x80>;
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};
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i2c@1700 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,mpc5121-i2c", "fsl-i2c";
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cell-index = <0>;
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reg = <0x1700 0x20>;
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interrupts = <9 0x8>;
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interrupt-parent = < &ipic >;
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fsl5200-clocking;
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};
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i2c@1720 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,mpc5121-i2c", "fsl-i2c";
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cell-index = <1>;
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reg = <0x1720 0x20>;
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interrupts = <10 0x8>;
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interrupt-parent = < &ipic >;
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fsl5200-clocking;
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};
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i2c@1740 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,mpc5121-i2c", "fsl-i2c";
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cell-index = <2>;
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reg = <0x1740 0x20>;
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interrupts = <11 0x8>;
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interrupt-parent = < &ipic >;
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fsl5200-clocking;
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};
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i2ccontrol@1760 {
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compatible = "fsl,mpc5121-i2c-ctrl";
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reg = <0x1760 0x8>;
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};
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axe@2000 {
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compatible = "fsl,mpc5121-axe";
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reg = <0x2000 0x100>;
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interrupts = <42 0x8>;
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interrupt-parent = < &ipic >;
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};
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display@2100 {
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compatible = "fsl,mpc5121-diu", "fsl-diu";
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reg = <0x2100 0x100>;
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interrupts = <64 0x8>;
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interrupt-parent = < &ipic >;
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};
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mdio@2800 {
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compatible = "fsl,mpc5121-fec-mdio";
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reg = <0x2800 0x800>;
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#address-cells = <1>;
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#size-cells = <0>;
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phy: ethernet-phy@0 {
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reg = <1>;
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device_type = "ethernet-phy";
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};
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};
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ethernet@2800 {
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device_type = "network";
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compatible = "fsl,mpc5121-fec";
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reg = <0x2800 0x800>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <4 0x8>;
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interrupt-parent = < &ipic >;
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phy-handle = < &phy >;
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fsl,align-tx-packets = <4>;
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};
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// 5121e has two dr usb modules
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// mpc5121_ads only uses USB0
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// USB1 using external ULPI PHY
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//usb@3000 {
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// compatible = "fsl,mpc5121-usb2-dr", "fsl-usb2-dr";
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// reg = <0x3000 0x1000>;
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// #address-cells = <1>;
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// #size-cells = <0>;
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// interrupt-parent = < &ipic >;
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// interrupts = <43 0x8>;
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// dr_mode = "otg";
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// phy_type = "ulpi";
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// port1;
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//};
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// USB0 using internal UTMI PHY
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usb@4000 {
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compatible = "fsl,mpc5121-usb2-dr", "fsl-usb2-dr";
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reg = <0x4000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupt-parent = < &ipic >;
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interrupts = <44 0x8>;
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dr_mode = "otg";
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phy_type = "utmi_wide";
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port0;
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};
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// IO control
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ioctl@a000 {
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compatible = "fsl,mpc5121-ioctl";
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reg = <0xA000 0x1000>;
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};
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pata@10200 {
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compatible = "fsl,mpc5121-pata";
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reg = <0x10200 0x100>;
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interrupts = <5 0x8>;
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interrupt-parent = < &ipic >;
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};
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// 512x PSCs are not 52xx PSC compatible
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// PSC3 serial port A aka ttyPSC0
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serial@11300 {
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device_type = "serial";
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compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
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// Logical port assignment needed until driver
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// learns to use aliases
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port-number = <0>;
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cell-index = <3>;
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reg = <0x11300 0x100>;
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interrupts = <40 0x8>;
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interrupt-parent = < &ipic >;
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rx-fifo-size = <16>;
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tx-fifo-size = <16>;
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};
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// PSC4 serial port B aka ttyPSC1
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serial@11400 {
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device_type = "serial";
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compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
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// Logical port assignment needed until driver
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// learns to use aliases
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port-number = <1>;
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cell-index = <4>;
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reg = <0x11400 0x100>;
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interrupts = <40 0x8>;
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interrupt-parent = < &ipic >;
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rx-fifo-size = <16>;
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tx-fifo-size = <16>;
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};
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// PSC5 in ac97 mode
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ac97@11500 {
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compatible = "fsl,mpc5121-psc-ac97", "fsl,mpc5121-psc";
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cell-index = <5>;
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reg = <0x11500 0x100>;
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interrupts = <40 0x8>;
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interrupt-parent = < &ipic >;
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fsl,mode = "ac97-slave";
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rx-fifo-size = <384>;
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tx-fifo-size = <384>;
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};
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pscfifo@11f00 {
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compatible = "fsl,mpc5121-psc-fifo";
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reg = <0x11f00 0x100>;
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interrupts = <40 0x8>;
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interrupt-parent = < &ipic >;
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};
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dma@14000 {
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compatible = "fsl,mpc5121-dma2";
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reg = <0x14000 0x1800>;
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interrupts = <65 0x8>;
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interrupt-parent = < &ipic >;
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};
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};
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pci: pci@80008500 {
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interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
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interrupt-map = <
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// IDSEL 0x15 - Slot 1 PCI
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0xa800 0x0 0x0 0x1 &cpld_pic 0x0 0x8
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0xa800 0x0 0x0 0x2 &cpld_pic 0x1 0x8
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0xa800 0x0 0x0 0x3 &cpld_pic 0x2 0x8
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0xa800 0x0 0x0 0x4 &cpld_pic 0x3 0x8
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// IDSEL 0x16 - Slot 2 MiniPCI
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0xb000 0x0 0x0 0x1 &cpld_pic 0x4 0x8
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0xb000 0x0 0x0 0x2 &cpld_pic 0x5 0x8
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// IDSEL 0x17 - Slot 3 MiniPCI
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0xb800 0x0 0x0 0x1 &cpld_pic 0x6 0x8
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0xb800 0x0 0x0 0x2 &cpld_pic 0x7 0x8
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>;
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interrupt-parent = < &ipic >;
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interrupts = <1 0x8>;
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bus-range = <0 0>;
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ranges = <0x42000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
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0x02000000 0x0 0xb0000000 0xb0000000 0x0 0x10000000
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0x01000000 0x0 0x00000000 0x84000000 0x0 0x01000000>;
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clock-frequency = <0>;
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <0x80008500 0x100>;
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compatible = "fsl,mpc5121-pci";
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device_type = "pci";
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};
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};
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