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07ffee59a7
Create separate functions to deal with instruction and data cache flushing. This way we can optimize them for the vairous cache types and arrangements used across the ColdFire family. For example the unified caches in the version 3 cores means we don't need to flush the instruction cache. For the version 2 cores that do not do data cacheing (or where we choose instruction cache only) we don't need to do any data flushing. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
102 lines
3.5 KiB
C
102 lines
3.5 KiB
C
/****************************************************************************/
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/*
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* m53xxacr.h -- ColdFire version 3 core cache support
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*
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* (C) Copyright 2010, Greg Ungerer <gerg@snapgear.com>
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*/
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/****************************************************************************/
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#ifndef m53xxacr_h
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#define m53xxacr_h
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/****************************************************************************/
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/*
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* All varients of the ColdFire using version 3 cores have a similar
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* cache setup. They have a unified instruction and data cache, with
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* configurable write-through or copy-back operation.
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*/
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/*
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* Define the Cache Control register flags.
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*/
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#define CACR_EC 0x80000000 /* Enable cache */
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#define CACR_ESB 0x20000000 /* Enable store buffer */
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#define CACR_DPI 0x10000000 /* Disable invalidation by CPUSHL */
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#define CACR_HLCK 0x08000000 /* Half cache lock mode */
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#define CACR_CINVA 0x01000000 /* Invalidate cache */
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#define CACR_DNFB 0x00000400 /* Inhibited fill buffer */
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#define CACR_DCM_WT 0x00000000 /* Cacheable write-through */
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#define CACR_DCM_CB 0x00000100 /* Cacheable copy-back */
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#define CACR_DCM_PRE 0x00000200 /* Cache inhibited, precise */
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#define CACR_DCM_IMPRE 0x00000300 /* Cache inhibited, imprecise */
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#define CACR_WPROTECT 0x00000020 /* Write protect*/
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#define CACR_EUSP 0x00000010 /* Eanble separate user a7 */
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/*
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* Define the Access Control register flags.
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*/
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#define ACR_BASE_POS 24 /* Address Base (upper 8 bits) */
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#define ACR_MASK_POS 16 /* Address Mask (next 8 bits) */
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#define ACR_ENABLE 0x00008000 /* Enable this ACR */
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#define ACR_USER 0x00000000 /* Allow only user accesses */
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#define ACR_SUPER 0x00002000 /* Allow supervisor access only */
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#define ACR_ANY 0x00004000 /* Allow any access type */
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#define ACR_CM_WT 0x00000000 /* Cacheable, write-through */
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#define ACR_CM_CB 0x00000020 /* Cacheable, copy-back */
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#define ACR_CM_PRE 0x00000040 /* Cache inhibited, precise */
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#define ACR_CM_IMPRE 0x00000060 /* Cache inhibited, imprecise */
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#define ACR_WPROTECT 0x00000004 /* Write protect region */
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/*
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* Define the cache type and arrangement (needed for pushes).
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*/
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#if defined(CONFIG_M5307)
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#define CACHE_SIZE 0x2000 /* 8k of unified cache */
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#define ICACHE_SIZE CACHE_SIZE
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#define DCACHE_SIZE CACHE_SIZE
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#elif defined(CONFIG_M532x)
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#define CACHE_SIZE 0x4000 /* 32k of unified cache */
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#define ICACHE_SIZE CACHE_SIZE
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#define DCACHE_SIZE CACHE_SIZE
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#endif
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#define CACHE_LINE_SIZE 16 /* 16 byte line size */
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#define CACHE_WAYS 4 /* 4 ways - set associative */
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/*
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* Set the cache controller settings we will use. This default in the
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* CACR is cache inhibited, we use the ACR register to set cacheing
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* enabled on the regions we want (eg RAM).
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*/
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#if defined(CONFIG_CACHE_COPYBACK)
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#define CACHE_TYPE ACR_CM_CB
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#define CACHE_PUSH
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#else
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#define CACHE_TYPE ACR_CM_WT
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#endif
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#ifdef CONFIG_COLDFIRE_SW_A7
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#define CACHE_MODE (CACR_EC + CACR_ESB + CACR_DCM_PRE)
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#else
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#define CACHE_MODE (CACR_EC + CACR_ESB + CACR_DCM_PRE + CACR_EUSP)
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#endif
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/*
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* Unified cache means we will never need to flush for coherency of
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* instruction fetch. We will need to flush to maintain memory/DMA
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* coherency though in all cases. And for copyback caches we will need
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* to push cached data as well.
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*/
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#define CACHE_INIT CACR_CINVA
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#define CACHE_INVALIDATE CACR_CINVA
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#define CACHE_INVALIDATED CACR_CINVA
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#define ACR0_MODE ((CONFIG_RAMBASE & 0xff000000) + \
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(0x000f0000) + \
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(ACR_ENABLE + ACR_ANY + CACHE_TYPE))
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#define ACR1_MODE 0
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/****************************************************************************/
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#endif /* m53xxsim_h */
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