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On CPUs with 64-byte last level cache lines, this yields roughly 10% better performance, independent of CPU vendor or specific model (as far as I was able to test). Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: H. Peter Anvin <hpa@zytor.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Link: http://lkml.kernel.org/r/5093E4B802000078000A615E@nat28.tlf.novell.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
28 lines
677 B
C
28 lines
677 B
C
#ifndef _ASM_X86_XOR_64_H
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#define _ASM_X86_XOR_64_H
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static struct xor_block_template xor_block_sse = {
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.name = "generic_sse",
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.do_2 = xor_sse_2,
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.do_3 = xor_sse_3,
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.do_4 = xor_sse_4,
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.do_5 = xor_sse_5,
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};
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/* Also try the AVX routines */
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#include <asm/xor_avx.h>
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/* We force the use of the SSE xor block because it can write around L2.
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We may also be able to load into the L1 only depending on how the cpu
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deals with a load to a line that is being prefetched. */
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#undef XOR_TRY_TEMPLATES
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#define XOR_TRY_TEMPLATES \
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do { \
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AVX_XOR_SPEED; \
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xor_speed(&xor_block_sse_pf64); \
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xor_speed(&xor_block_sse); \
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} while (0)
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#endif /* _ASM_X86_XOR_64_H */
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