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19855c8276
Until now (gx and axg), the mpll setting on boot (whatever the bootloader) was good enough to generate a clean fractional division. It is not the case on the g12a. While moving away from the vendor u-boot, it was noticed the fractional part of the divider was no longer applied. Like on the pll, some magic settings need to applied on the mpll register. This change adds the ability to do that on the mpll driver. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
34 lines
712 B
C
34 lines
712 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 BayLibre, SAS.
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* Author: Jerome Brunet <jbrunet@baylibre.com>
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*/
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#ifndef __MESON_CLK_MPLL_H
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#define __MESON_CLK_MPLL_H
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#include <linux/clk-provider.h>
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#include <linux/spinlock.h>
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#include "parm.h"
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struct meson_clk_mpll_data {
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struct parm sdm;
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struct parm sdm_en;
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struct parm n2;
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struct parm ssen;
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struct parm misc;
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const struct reg_sequence *init_regs;
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unsigned int init_count;
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spinlock_t *lock;
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u8 flags;
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};
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#define CLK_MESON_MPLL_ROUND_CLOSEST BIT(0)
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#define CLK_MESON_MPLL_SPREAD_SPECTRUM BIT(1)
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extern const struct clk_ops meson_clk_mpll_ro_ops;
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extern const struct clk_ops meson_clk_mpll_ops;
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#endif /* __MESON_CLK_MPLL_H */
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