mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-26 06:04:14 +08:00
4625f1b5d4
hdmi driver needs to change the parent of hdmi clock to pixel clock or hdmiphy clock, based on the stability of hdmiphy. This patch is exposing the mux for changing the parent. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Acked-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
209 lines
3.7 KiB
Plaintext
209 lines
3.7 KiB
Plaintext
* Samsung Exynos5420 Clock Controller
|
|
|
|
The Exynos5420 clock controller generates and supplies clock to various
|
|
controllers within the Exynos5420 SoC.
|
|
|
|
Required Properties:
|
|
|
|
- comptible: should be one of the following.
|
|
- "samsung,exynos5420-clock" - controller compatible with Exynos5420 SoC.
|
|
|
|
- reg: physical base address of the controller and length of memory mapped
|
|
region.
|
|
|
|
- #clock-cells: should be 1.
|
|
|
|
The following is the list of clocks generated by the controller. Each clock is
|
|
assigned an identifier and client nodes use this identifier to specify the
|
|
clock which they consume.
|
|
|
|
|
|
[Core Clocks]
|
|
|
|
Clock ID
|
|
----------------------------
|
|
|
|
fin_pll 1
|
|
|
|
[Clock Gate for Special Clocks]
|
|
|
|
Clock ID
|
|
----------------------------
|
|
sclk_uart0 128
|
|
sclk_uart1 129
|
|
sclk_uart2 130
|
|
sclk_uart3 131
|
|
sclk_mmc0 132
|
|
sclk_mmc1 133
|
|
sclk_mmc2 134
|
|
sclk_spi0 135
|
|
sclk_spi1 136
|
|
sclk_spi2 137
|
|
sclk_i2s1 138
|
|
sclk_i2s2 139
|
|
sclk_pcm1 140
|
|
sclk_pcm2 141
|
|
sclk_spdif 142
|
|
sclk_hdmi 143
|
|
sclk_pixel 144
|
|
sclk_dp1 145
|
|
sclk_mipi1 146
|
|
sclk_fimd1 147
|
|
sclk_maudio0 148
|
|
sclk_maupcm0 149
|
|
sclk_usbd300 150
|
|
sclk_usbd301 151
|
|
sclk_usbphy300 152
|
|
sclk_usbphy301 153
|
|
sclk_unipro 154
|
|
sclk_pwm 155
|
|
sclk_gscl_wa 156
|
|
sclk_gscl_wb 157
|
|
sclk_hdmiphy 158
|
|
|
|
[Peripheral Clock Gates]
|
|
|
|
Clock ID
|
|
----------------------------
|
|
|
|
aclk66_peric 256
|
|
uart0 257
|
|
uart1 258
|
|
uart2 259
|
|
uart3 260
|
|
i2c0 261
|
|
i2c1 262
|
|
i2c2 263
|
|
i2c3 264
|
|
i2c4 265
|
|
i2c5 266
|
|
i2c6 267
|
|
i2c7 268
|
|
i2c_hdmi 269
|
|
tsadc 270
|
|
spi0 271
|
|
spi1 272
|
|
spi2 273
|
|
keyif 274
|
|
i2s1 275
|
|
i2s2 276
|
|
pcm1 277
|
|
pcm2 278
|
|
pwm 279
|
|
spdif 280
|
|
i2c8 281
|
|
i2c9 282
|
|
i2c10 283
|
|
aclk66_psgen 300
|
|
chipid 301
|
|
sysreg 302
|
|
tzpc0 303
|
|
tzpc1 304
|
|
tzpc2 305
|
|
tzpc3 306
|
|
tzpc4 307
|
|
tzpc5 308
|
|
tzpc6 309
|
|
tzpc7 310
|
|
tzpc8 311
|
|
tzpc9 312
|
|
hdmi_cec 313
|
|
seckey 314
|
|
mct 315
|
|
wdt 316
|
|
rtc 317
|
|
tmu 318
|
|
tmu_gpu 319
|
|
pclk66_gpio 330
|
|
aclk200_fsys2 350
|
|
mmc0 351
|
|
mmc1 352
|
|
mmc2 353
|
|
sromc 354
|
|
ufs 355
|
|
aclk200_fsys 360
|
|
tsi 361
|
|
pdma0 362
|
|
pdma1 363
|
|
rtic 364
|
|
usbh20 365
|
|
usbd300 366
|
|
usbd301 377
|
|
aclk400_mscl 380
|
|
mscl0 381
|
|
mscl1 382
|
|
mscl2 383
|
|
smmu_mscl0 384
|
|
smmu_mscl1 385
|
|
smmu_mscl2 386
|
|
aclk333 400
|
|
mfc 401
|
|
smmu_mfcl 402
|
|
smmu_mfcr 403
|
|
aclk200_disp1 410
|
|
dsim1 411
|
|
dp1 412
|
|
hdmi 413
|
|
aclk300_disp1 420
|
|
fimd1 421
|
|
smmu_fimd1 422
|
|
aclk166 430
|
|
mixer 431
|
|
aclk266 440
|
|
rotator 441
|
|
mdma1 442
|
|
smmu_rotator 443
|
|
smmu_mdma1 444
|
|
aclk300_jpeg 450
|
|
jpeg 451
|
|
jpeg2 452
|
|
smmu_jpeg 453
|
|
aclk300_gscl 460
|
|
smmu_gscl0 461
|
|
smmu_gscl1 462
|
|
gscl_wa 463
|
|
gscl_wb 464
|
|
gscl0 465
|
|
gscl1 466
|
|
clk_3aa 467
|
|
aclk266_g2d 470
|
|
sss 471
|
|
slim_sss 472
|
|
mdma0 473
|
|
aclk333_g2d 480
|
|
g2d 481
|
|
aclk333_432_gscl 490
|
|
smmu_3aa 491
|
|
smmu_fimcl0 492
|
|
smmu_fimcl1 493
|
|
smmu_fimcl3 494
|
|
fimc_lite3 495
|
|
aclk_g3d 500
|
|
g3d 501
|
|
smmu_mixer 502
|
|
|
|
Mux ID
|
|
----------------------------
|
|
|
|
mout_hdmi 640
|
|
|
|
Example 1: An example of a clock controller node is listed below.
|
|
|
|
clock: clock-controller@0x10010000 {
|
|
compatible = "samsung,exynos5420-clock";
|
|
reg = <0x10010000 0x30000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
Example 2: UART controller node that consumes the clock generated by the clock
|
|
controller. Refer to the standard clock bindings for information
|
|
about 'clocks' and 'clock-names' property.
|
|
|
|
serial@13820000 {
|
|
compatible = "samsung,exynos4210-uart";
|
|
reg = <0x13820000 0x100>;
|
|
interrupts = <0 54 0>;
|
|
clocks = <&clock 259>, <&clock 130>;
|
|
clock-names = "uart", "clk_uart_baud0";
|
|
};
|