Josh Cartwright 45aa2c27ad clk: Add support for fundamental zynq clks ... Provide simplified models for the necessary clocks on the zynq-7000 platform. Currently, the PLLs, the CPU clock network, and the basic peripheral clock networks (for SDIO, SMC, SPI, QSPI, UART) are modelled. OF bindings are also provided and documented. Signed-off-by: Josh Cartwright <josh.cartwright@ni.com> Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Michal Simek <michal.simek@xilinx.com>		2012-11-14 16:07:55 +01:00
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calxeda.txt	clk: add highbank clock support	2012-07-11 17:58:47 -07:00
clock-bindings.txt
fixed-clock.txt
imx6q-clock.txt	ARM: imx6q: replace clk_register_clkdev with clock DT lookup	2012-09-11 19:16:14 +08:00
imx23-clock.txt	clk: mxs: replace imx23 clk_register_clkdev with clock DT lookup	2012-09-11 14:45:46 +08:00
imx28-clock.txt	clk: mxs: replace imx28 clk_register_clkdev with clock DT lookup	2012-09-11 14:45:46 +08:00
vt8500.txt	arm: vt8500: doc: Add device tree bindings for arch-vt8500 devices	2012-09-21 19:23:58 +12:00
zynq-7000.txt	clk: Add support for fundamental zynq clks	2012-11-14 16:07:55 +01:00