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76148ab8b7
All these separate directories for each ColdFire CPU SoC varient seems like overkill. The majority of them only contain a single small config file. Move these into the common ColdFire code directory. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
138 lines
3.4 KiB
C
138 lines
3.4 KiB
C
/***************************************************************************/
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/*
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* linux/arch/m68knommu/platform/528x/config.c
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*
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* Sub-architcture dependent initialization code for the Freescale
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* 5280, 5281 and 5282 CPUs.
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*
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* Copyright (C) 1999-2003, Greg Ungerer (gerg@snapgear.com)
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* Copyright (C) 2001-2003, SnapGear Inc. (www.snapgear.com)
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*/
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/***************************************************************************/
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#include <linux/kernel.h>
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#include <linux/param.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <asm/machdep.h>
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#include <asm/coldfire.h>
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#include <asm/mcfsim.h>
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#include <asm/mcfuart.h>
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#include <asm/mcfgpio.h>
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/***************************************************************************/
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struct mcf_gpio_chip mcf_gpio_chips[] = {
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MCFGPS(NQ, 1, 7, MCFEPORT_EPDDR, MCFEPORT_EPDR, MCFEPORT_EPPDR),
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MCFGPS(TA, 8, 4, MCFGPTA_GPTDDR, MCFGPTA_GPTPORT, MCFGPTB_GPTPORT),
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MCFGPS(TB, 16, 4, MCFGPTB_GPTDDR, MCFGPTB_GPTPORT, MCFGPTB_GPTPORT),
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MCFGPS(QA, 24, 4, MCFQADC_DDRQA, MCFQADC_PORTQA, MCFQADC_PORTQA),
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MCFGPS(QB, 32, 4, MCFQADC_DDRQB, MCFQADC_PORTQB, MCFQADC_PORTQB),
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MCFGPF(A, 40, 8),
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MCFGPF(B, 48, 8),
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MCFGPF(C, 56, 8),
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MCFGPF(D, 64, 8),
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MCFGPF(E, 72, 8),
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MCFGPF(F, 80, 8),
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MCFGPF(G, 88, 8),
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MCFGPF(H, 96, 8),
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MCFGPF(J, 104, 8),
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MCFGPF(DD, 112, 8),
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MCFGPF(EH, 120, 8),
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MCFGPF(EL, 128, 8),
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MCFGPF(AS, 136, 6),
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MCFGPF(QS, 144, 7),
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MCFGPF(SD, 152, 6),
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MCFGPF(TC, 160, 4),
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MCFGPF(TD, 168, 4),
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MCFGPF(UA, 176, 4),
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};
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unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips);
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/***************************************************************************/
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#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
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static void __init m528x_qspi_init(void)
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{
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/* setup Port QS for QSPI with gpio CS control */
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__raw_writeb(0x07, MCFGPIO_PQSPAR);
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}
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#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
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/***************************************************************************/
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static void __init m528x_uarts_init(void)
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{
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u8 port;
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/* make sure PUAPAR is set for UART0 and UART1 */
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port = readb(MCF5282_GPIO_PUAPAR);
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port |= 0x03 | (0x03 << 2);
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writeb(port, MCF5282_GPIO_PUAPAR);
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}
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/***************************************************************************/
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static void __init m528x_fec_init(void)
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{
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u16 v16;
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/* Set multi-function pins to ethernet mode for fec0 */
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v16 = readw(MCF_IPSBAR + 0x100056);
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writew(v16 | 0xf00, MCF_IPSBAR + 0x100056);
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writeb(0xc0, MCF_IPSBAR + 0x100058);
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}
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/***************************************************************************/
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#ifdef CONFIG_WILDFIRE
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void wildfire_halt(void)
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{
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writeb(0, 0x30000007);
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writeb(0x2, 0x30000007);
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}
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#endif
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#ifdef CONFIG_WILDFIREMOD
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void wildfiremod_halt(void)
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{
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printk(KERN_INFO "WildFireMod hibernating...\n");
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/* Set portE.5 to Digital IO */
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MCF5282_GPIO_PEPAR &= ~(1 << (5 * 2));
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/* Make portE.5 an output */
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MCF5282_GPIO_DDRE |= (1 << 5);
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/* Now toggle portE.5 from low to high */
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MCF5282_GPIO_PORTE &= ~(1 << 5);
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MCF5282_GPIO_PORTE |= (1 << 5);
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printk(KERN_EMERG "Failed to hibernate. Halting!\n");
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}
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#endif
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void __init config_BSP(char *commandp, int size)
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{
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#ifdef CONFIG_WILDFIRE
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mach_halt = wildfire_halt;
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#endif
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#ifdef CONFIG_WILDFIREMOD
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mach_halt = wildfiremod_halt;
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#endif
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mach_sched_init = hw_timer_init;
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m528x_uarts_init();
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m528x_fec_init();
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#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
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m528x_qspi_init();
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#endif
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}
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/***************************************************************************/
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