Imre Deak 447811a686 drm/i915/icl: Fix MG_DP_MODE() register programming ... Fix the order of lane, port parameters passed to the register macro. Note that this was already partly fixed by commit 37fc7845df ("drm/i915: Call MG_DP_MODE() macro with the right parameters order") While at it simplify things by using the macro directly instead of an unnecessary redirection via an array. v2: - Add a note the commit message about simplifying things. (José) Fixes: 58106b7d81 ("drm/i915: Make MG PHY macros semantically consistent") Cc: José Roberto de Souza <jose.souza@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Aditya Swarup <aditya.swarup@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190419071026.32370-1-imre.deak@intel.com (cherry picked from commit 9c11b12184) Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>		2019-04-24 09:39:11 +03:00
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drm	drm/i915/icl: Fix MG_DP_MODE() register programming	2019-04-24 09:39:11 +03:00
host1x	gpu: host1x: Fix compile error when IOMMU API is not available	2019-04-11 10:35:39 +02:00
ipu-v3	media updates for v5.1-rc1	2019-03-09 14:45:54 -08:00
vga	- qxl: Remove the conflicting framebuffers earlier	2019-03-14 11:37:46 +10:00
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