mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-25 21:54:06 +08:00
4d2fa8b44b
Pull crypto updates from Herbert Xu: "Here is the crypto update for 5.3: API: - Test shash interface directly in testmgr - cra_driver_name is now mandatory Algorithms: - Replace arc4 crypto_cipher with library helper - Implement 5 way interleave for ECB, CBC and CTR on arm64 - Add xxhash - Add continuous self-test on noise source to drbg - Update jitter RNG Drivers: - Add support for SHA204A random number generator - Add support for 7211 in iproc-rng200 - Fix fuzz test failures in inside-secure - Fix fuzz test failures in talitos - Fix fuzz test failures in qat" * 'linus' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6: (143 commits) crypto: stm32/hash - remove interruptible condition for dma crypto: stm32/hash - Fix hmac issue more than 256 bytes crypto: stm32/crc32 - rename driver file crypto: amcc - remove memset after dma_alloc_coherent crypto: ccp - Switch to SPDX license identifiers crypto: ccp - Validate the the error value used to index error messages crypto: doc - Fix formatting of new crypto engine content crypto: doc - Add parameter documentation crypto: arm64/aes-ce - implement 5 way interleave for ECB, CBC and CTR crypto: arm64/aes-ce - add 5 way interleave routines crypto: talitos - drop icv_ool crypto: talitos - fix hash on SEC1. crypto: talitos - move struct talitos_edesc into talitos.h lib/scatterlist: Fix mapping iterator when sg->offset is greater than PAGE_SIZE crypto/NX: Set receive window credits to max number of CRBs in RxFIFO crypto: asymmetric_keys - select CRYPTO_HASH where needed crypto: serpent - mark __serpent_setkey_sbox noinline crypto: testmgr - dynamically allocate crypto_shash crypto: testmgr - dynamically allocate testvec_config crypto: talitos - eliminate unneeded 'done' functions at build time ...
1062 lines
27 KiB
C
1062 lines
27 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Driver for IBM PowerNV 842 compression accelerator
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*
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* Copyright (C) 2015 Dan Streetman, IBM Corp
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include "nx-842.h"
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#include <linux/timer.h>
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#include <asm/prom.h>
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#include <asm/icswx.h>
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#include <asm/vas.h>
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#include <asm/reg.h>
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#include <asm/opal-api.h>
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#include <asm/opal.h>
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("Dan Streetman <ddstreet@ieee.org>");
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MODULE_DESCRIPTION("842 H/W Compression driver for IBM PowerNV processors");
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MODULE_ALIAS_CRYPTO("842");
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MODULE_ALIAS_CRYPTO("842-nx");
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#define WORKMEM_ALIGN (CRB_ALIGN)
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#define CSB_WAIT_MAX (5000) /* ms */
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#define VAS_RETRIES (10)
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struct nx842_workmem {
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/* Below fields must be properly aligned */
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struct coprocessor_request_block crb; /* CRB_ALIGN align */
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struct data_descriptor_entry ddl_in[DDL_LEN_MAX]; /* DDE_ALIGN align */
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struct data_descriptor_entry ddl_out[DDL_LEN_MAX]; /* DDE_ALIGN align */
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/* Above fields must be properly aligned */
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ktime_t start;
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char padding[WORKMEM_ALIGN]; /* unused, to allow alignment */
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} __packed __aligned(WORKMEM_ALIGN);
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struct nx842_coproc {
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unsigned int chip_id;
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unsigned int ct;
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unsigned int ci; /* Coprocessor instance, used with icswx */
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struct {
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struct vas_window *rxwin;
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int id;
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} vas;
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struct list_head list;
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};
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/*
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* Send the request to NX engine on the chip for the corresponding CPU
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* where the process is executing. Use with VAS function.
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*/
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static DEFINE_PER_CPU(struct vas_window *, cpu_txwin);
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/* no cpu hotplug on powernv, so this list never changes after init */
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static LIST_HEAD(nx842_coprocs);
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static unsigned int nx842_ct; /* used in icswx function */
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static int (*nx842_powernv_exec)(const unsigned char *in,
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unsigned int inlen, unsigned char *out,
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unsigned int *outlenp, void *workmem, int fc);
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/**
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* setup_indirect_dde - Setup an indirect DDE
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*
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* The DDE is setup with the the DDE count, byte count, and address of
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* first direct DDE in the list.
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*/
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static void setup_indirect_dde(struct data_descriptor_entry *dde,
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struct data_descriptor_entry *ddl,
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unsigned int dde_count, unsigned int byte_count)
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{
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dde->flags = 0;
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dde->count = dde_count;
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dde->index = 0;
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dde->length = cpu_to_be32(byte_count);
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dde->address = cpu_to_be64(nx842_get_pa(ddl));
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}
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/**
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* setup_direct_dde - Setup single DDE from buffer
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*
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* The DDE is setup with the buffer and length. The buffer must be properly
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* aligned. The used length is returned.
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* Returns:
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* N Successfully set up DDE with N bytes
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*/
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static unsigned int setup_direct_dde(struct data_descriptor_entry *dde,
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unsigned long pa, unsigned int len)
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{
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unsigned int l = min_t(unsigned int, len, LEN_ON_PAGE(pa));
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dde->flags = 0;
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dde->count = 0;
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dde->index = 0;
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dde->length = cpu_to_be32(l);
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dde->address = cpu_to_be64(pa);
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return l;
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}
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/**
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* setup_ddl - Setup DDL from buffer
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*
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* Returns:
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* 0 Successfully set up DDL
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*/
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static int setup_ddl(struct data_descriptor_entry *dde,
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struct data_descriptor_entry *ddl,
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unsigned char *buf, unsigned int len,
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bool in)
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{
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unsigned long pa = nx842_get_pa(buf);
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int i, ret, total_len = len;
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if (!IS_ALIGNED(pa, DDE_BUFFER_ALIGN)) {
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pr_debug("%s buffer pa 0x%lx not 0x%x-byte aligned\n",
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in ? "input" : "output", pa, DDE_BUFFER_ALIGN);
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return -EINVAL;
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}
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/* only need to check last mult; since buffer must be
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* DDE_BUFFER_ALIGN aligned, and that is a multiple of
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* DDE_BUFFER_SIZE_MULT, and pre-last page DDE buffers
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* are guaranteed a multiple of DDE_BUFFER_SIZE_MULT.
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*/
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if (len % DDE_BUFFER_LAST_MULT) {
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pr_debug("%s buffer len 0x%x not a multiple of 0x%x\n",
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in ? "input" : "output", len, DDE_BUFFER_LAST_MULT);
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if (in)
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return -EINVAL;
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len = round_down(len, DDE_BUFFER_LAST_MULT);
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}
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/* use a single direct DDE */
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if (len <= LEN_ON_PAGE(pa)) {
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ret = setup_direct_dde(dde, pa, len);
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WARN_ON(ret < len);
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return 0;
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}
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/* use the DDL */
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for (i = 0; i < DDL_LEN_MAX && len > 0; i++) {
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ret = setup_direct_dde(&ddl[i], pa, len);
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buf += ret;
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len -= ret;
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pa = nx842_get_pa(buf);
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}
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if (len > 0) {
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pr_debug("0x%x total %s bytes 0x%x too many for DDL.\n",
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total_len, in ? "input" : "output", len);
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if (in)
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return -EMSGSIZE;
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total_len -= len;
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}
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setup_indirect_dde(dde, ddl, i, total_len);
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return 0;
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}
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#define CSB_ERR(csb, msg, ...) \
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pr_err("ERROR: " msg " : %02x %02x %02x %02x %08x\n", \
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##__VA_ARGS__, (csb)->flags, \
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(csb)->cs, (csb)->cc, (csb)->ce, \
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be32_to_cpu((csb)->count))
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#define CSB_ERR_ADDR(csb, msg, ...) \
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CSB_ERR(csb, msg " at %lx", ##__VA_ARGS__, \
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(unsigned long)be64_to_cpu((csb)->address))
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/**
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* wait_for_csb
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*/
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static int wait_for_csb(struct nx842_workmem *wmem,
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struct coprocessor_status_block *csb)
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{
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ktime_t start = wmem->start, now = ktime_get();
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ktime_t timeout = ktime_add_ms(start, CSB_WAIT_MAX);
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while (!(READ_ONCE(csb->flags) & CSB_V)) {
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cpu_relax();
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now = ktime_get();
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if (ktime_after(now, timeout))
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break;
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}
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/* hw has updated csb and output buffer */
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barrier();
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/* check CSB flags */
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if (!(csb->flags & CSB_V)) {
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CSB_ERR(csb, "CSB still not valid after %ld us, giving up",
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(long)ktime_us_delta(now, start));
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return -ETIMEDOUT;
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}
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if (csb->flags & CSB_F) {
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CSB_ERR(csb, "Invalid CSB format");
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return -EPROTO;
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}
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if (csb->flags & CSB_CH) {
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CSB_ERR(csb, "Invalid CSB chaining state");
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return -EPROTO;
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}
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/* verify CSB completion sequence is 0 */
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if (csb->cs) {
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CSB_ERR(csb, "Invalid CSB completion sequence");
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return -EPROTO;
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}
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/* check CSB Completion Code */
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switch (csb->cc) {
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/* no error */
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case CSB_CC_SUCCESS:
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break;
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case CSB_CC_TPBC_GT_SPBC:
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/* not an error, but the compressed data is
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* larger than the uncompressed data :(
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*/
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break;
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/* input data errors */
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case CSB_CC_OPERAND_OVERLAP:
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/* input and output buffers overlap */
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CSB_ERR(csb, "Operand Overlap error");
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return -EINVAL;
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case CSB_CC_INVALID_OPERAND:
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CSB_ERR(csb, "Invalid operand");
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return -EINVAL;
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case CSB_CC_NOSPC:
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/* output buffer too small */
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return -ENOSPC;
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case CSB_CC_ABORT:
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CSB_ERR(csb, "Function aborted");
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return -EINTR;
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case CSB_CC_CRC_MISMATCH:
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CSB_ERR(csb, "CRC mismatch");
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return -EINVAL;
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case CSB_CC_TEMPL_INVALID:
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CSB_ERR(csb, "Compressed data template invalid");
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return -EINVAL;
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case CSB_CC_TEMPL_OVERFLOW:
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CSB_ERR(csb, "Compressed data template shows data past end");
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return -EINVAL;
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case CSB_CC_EXCEED_BYTE_COUNT: /* P9 or later */
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/*
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* DDE byte count exceeds the limit specified in Maximum
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* byte count register.
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*/
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CSB_ERR(csb, "DDE byte count exceeds the limit");
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return -EINVAL;
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/* these should not happen */
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case CSB_CC_INVALID_ALIGN:
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/* setup_ddl should have detected this */
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CSB_ERR_ADDR(csb, "Invalid alignment");
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return -EINVAL;
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case CSB_CC_DATA_LENGTH:
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/* setup_ddl should have detected this */
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CSB_ERR(csb, "Invalid data length");
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return -EINVAL;
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case CSB_CC_WR_TRANSLATION:
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case CSB_CC_TRANSLATION:
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case CSB_CC_TRANSLATION_DUP1:
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case CSB_CC_TRANSLATION_DUP2:
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case CSB_CC_TRANSLATION_DUP3:
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case CSB_CC_TRANSLATION_DUP4:
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case CSB_CC_TRANSLATION_DUP5:
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case CSB_CC_TRANSLATION_DUP6:
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/* should not happen, we use physical addrs */
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CSB_ERR_ADDR(csb, "Translation error");
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return -EPROTO;
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case CSB_CC_WR_PROTECTION:
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case CSB_CC_PROTECTION:
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case CSB_CC_PROTECTION_DUP1:
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case CSB_CC_PROTECTION_DUP2:
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case CSB_CC_PROTECTION_DUP3:
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case CSB_CC_PROTECTION_DUP4:
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case CSB_CC_PROTECTION_DUP5:
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case CSB_CC_PROTECTION_DUP6:
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/* should not happen, we use physical addrs */
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CSB_ERR_ADDR(csb, "Protection error");
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return -EPROTO;
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case CSB_CC_PRIVILEGE:
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/* shouldn't happen, we're in HYP mode */
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CSB_ERR(csb, "Insufficient Privilege error");
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return -EPROTO;
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case CSB_CC_EXCESSIVE_DDE:
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/* shouldn't happen, setup_ddl doesn't use many dde's */
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CSB_ERR(csb, "Too many DDEs in DDL");
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return -EINVAL;
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case CSB_CC_TRANSPORT:
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case CSB_CC_INVALID_CRB: /* P9 or later */
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/* shouldn't happen, we setup CRB correctly */
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CSB_ERR(csb, "Invalid CRB");
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return -EINVAL;
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case CSB_CC_INVALID_DDE: /* P9 or later */
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/*
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* shouldn't happen, setup_direct/indirect_dde creates
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* DDE right
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*/
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CSB_ERR(csb, "Invalid DDE");
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return -EINVAL;
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case CSB_CC_SEGMENTED_DDL:
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/* shouldn't happen, setup_ddl creates DDL right */
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CSB_ERR(csb, "Segmented DDL error");
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return -EINVAL;
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case CSB_CC_DDE_OVERFLOW:
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/* shouldn't happen, setup_ddl creates DDL right */
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CSB_ERR(csb, "DDE overflow error");
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return -EINVAL;
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case CSB_CC_SESSION:
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/* should not happen with ICSWX */
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CSB_ERR(csb, "Session violation error");
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return -EPROTO;
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case CSB_CC_CHAIN:
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/* should not happen, we don't use chained CRBs */
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CSB_ERR(csb, "Chained CRB error");
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return -EPROTO;
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case CSB_CC_SEQUENCE:
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/* should not happen, we don't use chained CRBs */
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CSB_ERR(csb, "CRB sequence number error");
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return -EPROTO;
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case CSB_CC_UNKNOWN_CODE:
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CSB_ERR(csb, "Unknown subfunction code");
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return -EPROTO;
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/* hardware errors */
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case CSB_CC_RD_EXTERNAL:
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case CSB_CC_RD_EXTERNAL_DUP1:
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case CSB_CC_RD_EXTERNAL_DUP2:
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case CSB_CC_RD_EXTERNAL_DUP3:
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CSB_ERR_ADDR(csb, "Read error outside coprocessor");
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return -EPROTO;
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case CSB_CC_WR_EXTERNAL:
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CSB_ERR_ADDR(csb, "Write error outside coprocessor");
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return -EPROTO;
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case CSB_CC_INTERNAL:
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CSB_ERR(csb, "Internal error in coprocessor");
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return -EPROTO;
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case CSB_CC_PROVISION:
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CSB_ERR(csb, "Storage provision error");
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return -EPROTO;
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case CSB_CC_HW:
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CSB_ERR(csb, "Correctable hardware error");
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return -EPROTO;
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case CSB_CC_HW_EXPIRED_TIMER: /* P9 or later */
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CSB_ERR(csb, "Job did not finish within allowed time");
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return -EPROTO;
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default:
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CSB_ERR(csb, "Invalid CC %d", csb->cc);
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return -EPROTO;
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}
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/* check Completion Extension state */
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if (csb->ce & CSB_CE_TERMINATION) {
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CSB_ERR(csb, "CSB request was terminated");
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return -EPROTO;
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}
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if (csb->ce & CSB_CE_INCOMPLETE) {
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CSB_ERR(csb, "CSB request not complete");
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return -EPROTO;
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}
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if (!(csb->ce & CSB_CE_TPBC)) {
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CSB_ERR(csb, "TPBC not provided, unknown target length");
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return -EPROTO;
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}
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/* successful completion */
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pr_debug_ratelimited("Processed %u bytes in %lu us\n",
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be32_to_cpu(csb->count),
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(unsigned long)ktime_us_delta(now, start));
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return 0;
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}
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static int nx842_config_crb(const unsigned char *in, unsigned int inlen,
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unsigned char *out, unsigned int outlen,
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struct nx842_workmem *wmem)
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{
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struct coprocessor_request_block *crb;
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struct coprocessor_status_block *csb;
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u64 csb_addr;
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int ret;
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crb = &wmem->crb;
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csb = &crb->csb;
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/* Clear any previous values */
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memset(crb, 0, sizeof(*crb));
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/* set up DDLs */
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ret = setup_ddl(&crb->source, wmem->ddl_in,
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(unsigned char *)in, inlen, true);
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if (ret)
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return ret;
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ret = setup_ddl(&crb->target, wmem->ddl_out,
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out, outlen, false);
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if (ret)
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return ret;
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/* set up CRB's CSB addr */
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csb_addr = nx842_get_pa(csb) & CRB_CSB_ADDRESS;
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csb_addr |= CRB_CSB_AT; /* Addrs are phys */
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crb->csb_addr = cpu_to_be64(csb_addr);
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return 0;
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}
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/**
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* nx842_exec_icswx - compress/decompress data using the 842 algorithm
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*
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* (De)compression provided by the NX842 coprocessor on IBM PowerNV systems.
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* This compresses or decompresses the provided input buffer into the provided
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* output buffer.
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*
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* Upon return from this function @outlen contains the length of the
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* output data. If there is an error then @outlen will be 0 and an
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* error will be specified by the return code from this function.
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*
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* The @workmem buffer should only be used by one function call at a time.
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*
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* @in: input buffer pointer
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* @inlen: input buffer size
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* @out: output buffer pointer
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* @outlenp: output buffer size pointer
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* @workmem: working memory buffer pointer, size determined by
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* nx842_powernv_driver.workmem_size
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* @fc: function code, see CCW Function Codes in nx-842.h
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*
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* Returns:
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* 0 Success, output of length @outlenp stored in the buffer at @out
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* -ENODEV Hardware unavailable
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* -ENOSPC Output buffer is to small
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* -EMSGSIZE Input buffer too large
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|
* -EINVAL buffer constraints do not fix nx842_constraints
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* -EPROTO hardware error during operation
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|
* -ETIMEDOUT hardware did not complete operation in reasonable time
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* -EINTR operation was aborted
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|
*/
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static int nx842_exec_icswx(const unsigned char *in, unsigned int inlen,
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unsigned char *out, unsigned int *outlenp,
|
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void *workmem, int fc)
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{
|
|
struct coprocessor_request_block *crb;
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struct coprocessor_status_block *csb;
|
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struct nx842_workmem *wmem;
|
|
int ret;
|
|
u32 ccw;
|
|
unsigned int outlen = *outlenp;
|
|
|
|
wmem = PTR_ALIGN(workmem, WORKMEM_ALIGN);
|
|
|
|
*outlenp = 0;
|
|
|
|
/* shoudn't happen, we don't load without a coproc */
|
|
if (!nx842_ct) {
|
|
pr_err_ratelimited("coprocessor CT is 0");
|
|
return -ENODEV;
|
|
}
|
|
|
|
ret = nx842_config_crb(in, inlen, out, outlen, wmem);
|
|
if (ret)
|
|
return ret;
|
|
|
|
crb = &wmem->crb;
|
|
csb = &crb->csb;
|
|
|
|
/* set up CCW */
|
|
ccw = 0;
|
|
ccw = SET_FIELD(CCW_CT, ccw, nx842_ct);
|
|
ccw = SET_FIELD(CCW_CI_842, ccw, 0); /* use 0 for hw auto-selection */
|
|
ccw = SET_FIELD(CCW_FC_842, ccw, fc);
|
|
|
|
wmem->start = ktime_get();
|
|
|
|
/* do ICSWX */
|
|
ret = icswx(cpu_to_be32(ccw), crb);
|
|
|
|
pr_debug_ratelimited("icswx CR %x ccw %x crb->ccw %x\n", ret,
|
|
(unsigned int)ccw,
|
|
(unsigned int)be32_to_cpu(crb->ccw));
|
|
|
|
/*
|
|
* NX842 coprocessor sets 3rd bit in CR register with XER[S0].
|
|
* XER[S0] is the integer summary overflow bit which is nothing
|
|
* to do NX. Since this bit can be set with other return values,
|
|
* mask this bit.
|
|
*/
|
|
ret &= ~ICSWX_XERS0;
|
|
|
|
switch (ret) {
|
|
case ICSWX_INITIATED:
|
|
ret = wait_for_csb(wmem, csb);
|
|
break;
|
|
case ICSWX_BUSY:
|
|
pr_debug_ratelimited("842 Coprocessor busy\n");
|
|
ret = -EBUSY;
|
|
break;
|
|
case ICSWX_REJECTED:
|
|
pr_err_ratelimited("ICSWX rejected\n");
|
|
ret = -EPROTO;
|
|
break;
|
|
}
|
|
|
|
if (!ret)
|
|
*outlenp = be32_to_cpu(csb->count);
|
|
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* nx842_exec_vas - compress/decompress data using the 842 algorithm
|
|
*
|
|
* (De)compression provided by the NX842 coprocessor on IBM PowerNV systems.
|
|
* This compresses or decompresses the provided input buffer into the provided
|
|
* output buffer.
|
|
*
|
|
* Upon return from this function @outlen contains the length of the
|
|
* output data. If there is an error then @outlen will be 0 and an
|
|
* error will be specified by the return code from this function.
|
|
*
|
|
* The @workmem buffer should only be used by one function call at a time.
|
|
*
|
|
* @in: input buffer pointer
|
|
* @inlen: input buffer size
|
|
* @out: output buffer pointer
|
|
* @outlenp: output buffer size pointer
|
|
* @workmem: working memory buffer pointer, size determined by
|
|
* nx842_powernv_driver.workmem_size
|
|
* @fc: function code, see CCW Function Codes in nx-842.h
|
|
*
|
|
* Returns:
|
|
* 0 Success, output of length @outlenp stored in the buffer
|
|
* at @out
|
|
* -ENODEV Hardware unavailable
|
|
* -ENOSPC Output buffer is to small
|
|
* -EMSGSIZE Input buffer too large
|
|
* -EINVAL buffer constraints do not fix nx842_constraints
|
|
* -EPROTO hardware error during operation
|
|
* -ETIMEDOUT hardware did not complete operation in reasonable time
|
|
* -EINTR operation was aborted
|
|
*/
|
|
static int nx842_exec_vas(const unsigned char *in, unsigned int inlen,
|
|
unsigned char *out, unsigned int *outlenp,
|
|
void *workmem, int fc)
|
|
{
|
|
struct coprocessor_request_block *crb;
|
|
struct coprocessor_status_block *csb;
|
|
struct nx842_workmem *wmem;
|
|
struct vas_window *txwin;
|
|
int ret, i = 0;
|
|
u32 ccw;
|
|
unsigned int outlen = *outlenp;
|
|
|
|
wmem = PTR_ALIGN(workmem, WORKMEM_ALIGN);
|
|
|
|
*outlenp = 0;
|
|
|
|
crb = &wmem->crb;
|
|
csb = &crb->csb;
|
|
|
|
ret = nx842_config_crb(in, inlen, out, outlen, wmem);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ccw = 0;
|
|
ccw = SET_FIELD(CCW_FC_842, ccw, fc);
|
|
crb->ccw = cpu_to_be32(ccw);
|
|
|
|
do {
|
|
wmem->start = ktime_get();
|
|
preempt_disable();
|
|
txwin = this_cpu_read(cpu_txwin);
|
|
|
|
/*
|
|
* VAS copy CRB into L2 cache. Refer <asm/vas.h>.
|
|
* @crb and @offset.
|
|
*/
|
|
vas_copy_crb(crb, 0);
|
|
|
|
/*
|
|
* VAS paste previously copied CRB to NX.
|
|
* @txwin, @offset and @last (must be true).
|
|
*/
|
|
ret = vas_paste_crb(txwin, 0, 1);
|
|
preempt_enable();
|
|
/*
|
|
* Retry copy/paste function for VAS failures.
|
|
*/
|
|
} while (ret && (i++ < VAS_RETRIES));
|
|
|
|
if (ret) {
|
|
pr_err_ratelimited("VAS copy/paste failed\n");
|
|
return ret;
|
|
}
|
|
|
|
ret = wait_for_csb(wmem, csb);
|
|
if (!ret)
|
|
*outlenp = be32_to_cpu(csb->count);
|
|
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* nx842_powernv_compress - Compress data using the 842 algorithm
|
|
*
|
|
* Compression provided by the NX842 coprocessor on IBM PowerNV systems.
|
|
* The input buffer is compressed and the result is stored in the
|
|
* provided output buffer.
|
|
*
|
|
* Upon return from this function @outlen contains the length of the
|
|
* compressed data. If there is an error then @outlen will be 0 and an
|
|
* error will be specified by the return code from this function.
|
|
*
|
|
* @in: input buffer pointer
|
|
* @inlen: input buffer size
|
|
* @out: output buffer pointer
|
|
* @outlenp: output buffer size pointer
|
|
* @workmem: working memory buffer pointer, size determined by
|
|
* nx842_powernv_driver.workmem_size
|
|
*
|
|
* Returns: see @nx842_powernv_exec()
|
|
*/
|
|
static int nx842_powernv_compress(const unsigned char *in, unsigned int inlen,
|
|
unsigned char *out, unsigned int *outlenp,
|
|
void *wmem)
|
|
{
|
|
return nx842_powernv_exec(in, inlen, out, outlenp,
|
|
wmem, CCW_FC_842_COMP_CRC);
|
|
}
|
|
|
|
/**
|
|
* nx842_powernv_decompress - Decompress data using the 842 algorithm
|
|
*
|
|
* Decompression provided by the NX842 coprocessor on IBM PowerNV systems.
|
|
* The input buffer is decompressed and the result is stored in the
|
|
* provided output buffer.
|
|
*
|
|
* Upon return from this function @outlen contains the length of the
|
|
* decompressed data. If there is an error then @outlen will be 0 and an
|
|
* error will be specified by the return code from this function.
|
|
*
|
|
* @in: input buffer pointer
|
|
* @inlen: input buffer size
|
|
* @out: output buffer pointer
|
|
* @outlenp: output buffer size pointer
|
|
* @workmem: working memory buffer pointer, size determined by
|
|
* nx842_powernv_driver.workmem_size
|
|
*
|
|
* Returns: see @nx842_powernv_exec()
|
|
*/
|
|
static int nx842_powernv_decompress(const unsigned char *in, unsigned int inlen,
|
|
unsigned char *out, unsigned int *outlenp,
|
|
void *wmem)
|
|
{
|
|
return nx842_powernv_exec(in, inlen, out, outlenp,
|
|
wmem, CCW_FC_842_DECOMP_CRC);
|
|
}
|
|
|
|
static inline void nx842_add_coprocs_list(struct nx842_coproc *coproc,
|
|
int chipid)
|
|
{
|
|
coproc->chip_id = chipid;
|
|
INIT_LIST_HEAD(&coproc->list);
|
|
list_add(&coproc->list, &nx842_coprocs);
|
|
}
|
|
|
|
static struct vas_window *nx842_alloc_txwin(struct nx842_coproc *coproc)
|
|
{
|
|
struct vas_window *txwin = NULL;
|
|
struct vas_tx_win_attr txattr;
|
|
|
|
/*
|
|
* Kernel requests will be high priority. So open send
|
|
* windows only for high priority RxFIFO entries.
|
|
*/
|
|
vas_init_tx_win_attr(&txattr, coproc->ct);
|
|
txattr.lpid = 0; /* lpid is 0 for kernel requests */
|
|
txattr.pid = 0; /* pid is 0 for kernel requests */
|
|
|
|
/*
|
|
* Open a VAS send window which is used to send request to NX.
|
|
*/
|
|
txwin = vas_tx_win_open(coproc->vas.id, coproc->ct, &txattr);
|
|
if (IS_ERR(txwin))
|
|
pr_err("ibm,nx-842: Can not open TX window: %ld\n",
|
|
PTR_ERR(txwin));
|
|
|
|
return txwin;
|
|
}
|
|
|
|
/*
|
|
* Identify chip ID for each CPU, open send wndow for the corresponding NX
|
|
* engine and save txwin in percpu cpu_txwin.
|
|
* cpu_txwin is used in copy/paste operation for each compression /
|
|
* decompression request.
|
|
*/
|
|
static int nx842_open_percpu_txwins(void)
|
|
{
|
|
struct nx842_coproc *coproc, *n;
|
|
unsigned int i, chip_id;
|
|
|
|
for_each_possible_cpu(i) {
|
|
struct vas_window *txwin = NULL;
|
|
|
|
chip_id = cpu_to_chip_id(i);
|
|
|
|
list_for_each_entry_safe(coproc, n, &nx842_coprocs, list) {
|
|
/*
|
|
* Kernel requests use only high priority FIFOs. So
|
|
* open send windows for these FIFOs.
|
|
*/
|
|
|
|
if (coproc->ct != VAS_COP_TYPE_842_HIPRI)
|
|
continue;
|
|
|
|
if (coproc->chip_id == chip_id) {
|
|
txwin = nx842_alloc_txwin(coproc);
|
|
if (IS_ERR(txwin))
|
|
return PTR_ERR(txwin);
|
|
|
|
per_cpu(cpu_txwin, i) = txwin;
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (!per_cpu(cpu_txwin, i)) {
|
|
/* shouldn't happen, Each chip will have NX engine */
|
|
pr_err("NX engine is not available for CPU %d\n", i);
|
|
return -EINVAL;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int __init vas_cfg_coproc_info(struct device_node *dn, int chip_id,
|
|
int vasid, int *ct)
|
|
{
|
|
struct vas_window *rxwin = NULL;
|
|
struct vas_rx_win_attr rxattr;
|
|
struct nx842_coproc *coproc;
|
|
u32 lpid, pid, tid, fifo_size;
|
|
u64 rx_fifo;
|
|
const char *priority;
|
|
int ret;
|
|
|
|
ret = of_property_read_u64(dn, "rx-fifo-address", &rx_fifo);
|
|
if (ret) {
|
|
pr_err("Missing rx-fifo-address property\n");
|
|
return ret;
|
|
}
|
|
|
|
ret = of_property_read_u32(dn, "rx-fifo-size", &fifo_size);
|
|
if (ret) {
|
|
pr_err("Missing rx-fifo-size property\n");
|
|
return ret;
|
|
}
|
|
|
|
ret = of_property_read_u32(dn, "lpid", &lpid);
|
|
if (ret) {
|
|
pr_err("Missing lpid property\n");
|
|
return ret;
|
|
}
|
|
|
|
ret = of_property_read_u32(dn, "pid", &pid);
|
|
if (ret) {
|
|
pr_err("Missing pid property\n");
|
|
return ret;
|
|
}
|
|
|
|
ret = of_property_read_u32(dn, "tid", &tid);
|
|
if (ret) {
|
|
pr_err("Missing tid property\n");
|
|
return ret;
|
|
}
|
|
|
|
ret = of_property_read_string(dn, "priority", &priority);
|
|
if (ret) {
|
|
pr_err("Missing priority property\n");
|
|
return ret;
|
|
}
|
|
|
|
coproc = kzalloc(sizeof(*coproc), GFP_KERNEL);
|
|
if (!coproc)
|
|
return -ENOMEM;
|
|
|
|
if (!strcmp(priority, "High"))
|
|
coproc->ct = VAS_COP_TYPE_842_HIPRI;
|
|
else if (!strcmp(priority, "Normal"))
|
|
coproc->ct = VAS_COP_TYPE_842;
|
|
else {
|
|
pr_err("Invalid RxFIFO priority value\n");
|
|
ret = -EINVAL;
|
|
goto err_out;
|
|
}
|
|
|
|
vas_init_rx_win_attr(&rxattr, coproc->ct);
|
|
rxattr.rx_fifo = (void *)rx_fifo;
|
|
rxattr.rx_fifo_size = fifo_size;
|
|
rxattr.lnotify_lpid = lpid;
|
|
rxattr.lnotify_pid = pid;
|
|
rxattr.lnotify_tid = tid;
|
|
/*
|
|
* Maximum RX window credits can not be more than #CRBs in
|
|
* RxFIFO. Otherwise, can get checkstop if RxFIFO overruns.
|
|
*/
|
|
rxattr.wcreds_max = fifo_size / CRB_SIZE;
|
|
|
|
/*
|
|
* Open a VAS receice window which is used to configure RxFIFO
|
|
* for NX.
|
|
*/
|
|
rxwin = vas_rx_win_open(vasid, coproc->ct, &rxattr);
|
|
if (IS_ERR(rxwin)) {
|
|
ret = PTR_ERR(rxwin);
|
|
pr_err("setting RxFIFO with VAS failed: %d\n",
|
|
ret);
|
|
goto err_out;
|
|
}
|
|
|
|
coproc->vas.rxwin = rxwin;
|
|
coproc->vas.id = vasid;
|
|
nx842_add_coprocs_list(coproc, chip_id);
|
|
|
|
/*
|
|
* (lpid, pid, tid) combination has to be unique for each
|
|
* coprocessor instance in the system. So to make it
|
|
* unique, skiboot uses coprocessor type such as 842 or
|
|
* GZIP for pid and provides this value to kernel in pid
|
|
* device-tree property.
|
|
*/
|
|
*ct = pid;
|
|
|
|
return 0;
|
|
|
|
err_out:
|
|
kfree(coproc);
|
|
return ret;
|
|
}
|
|
|
|
|
|
static int __init nx842_powernv_probe_vas(struct device_node *pn)
|
|
{
|
|
struct device_node *dn;
|
|
int chip_id, vasid, ret = 0;
|
|
int nx_fifo_found = 0;
|
|
int uninitialized_var(ct);
|
|
|
|
chip_id = of_get_ibm_chip_id(pn);
|
|
if (chip_id < 0) {
|
|
pr_err("ibm,chip-id missing\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
vasid = chip_to_vas_id(chip_id);
|
|
if (vasid < 0) {
|
|
pr_err("Unable to map chip_id %d to vasid\n", chip_id);
|
|
return -EINVAL;
|
|
}
|
|
|
|
for_each_child_of_node(pn, dn) {
|
|
if (of_device_is_compatible(dn, "ibm,p9-nx-842")) {
|
|
ret = vas_cfg_coproc_info(dn, chip_id, vasid, &ct);
|
|
if (ret) {
|
|
of_node_put(dn);
|
|
return ret;
|
|
}
|
|
nx_fifo_found++;
|
|
}
|
|
}
|
|
|
|
if (!nx_fifo_found) {
|
|
pr_err("NX842 FIFO nodes are missing\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
/*
|
|
* Initialize NX instance for both high and normal priority FIFOs.
|
|
*/
|
|
if (opal_check_token(OPAL_NX_COPROC_INIT)) {
|
|
ret = opal_nx_coproc_init(chip_id, ct);
|
|
if (ret) {
|
|
pr_err("Failed to initialize NX for chip(%d): %d\n",
|
|
chip_id, ret);
|
|
ret = opal_error_code(ret);
|
|
}
|
|
} else
|
|
pr_warn("Firmware doesn't support NX initialization\n");
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int __init nx842_powernv_probe(struct device_node *dn)
|
|
{
|
|
struct nx842_coproc *coproc;
|
|
unsigned int ct, ci;
|
|
int chip_id;
|
|
|
|
chip_id = of_get_ibm_chip_id(dn);
|
|
if (chip_id < 0) {
|
|
pr_err("ibm,chip-id missing\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (of_property_read_u32(dn, "ibm,842-coprocessor-type", &ct)) {
|
|
pr_err("ibm,842-coprocessor-type missing\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (of_property_read_u32(dn, "ibm,842-coprocessor-instance", &ci)) {
|
|
pr_err("ibm,842-coprocessor-instance missing\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
coproc = kmalloc(sizeof(*coproc), GFP_KERNEL);
|
|
if (!coproc)
|
|
return -ENOMEM;
|
|
|
|
coproc->ct = ct;
|
|
coproc->ci = ci;
|
|
nx842_add_coprocs_list(coproc, chip_id);
|
|
|
|
pr_info("coprocessor found on chip %d, CT %d CI %d\n", chip_id, ct, ci);
|
|
|
|
if (!nx842_ct)
|
|
nx842_ct = ct;
|
|
else if (nx842_ct != ct)
|
|
pr_err("NX842 chip %d, CT %d != first found CT %d\n",
|
|
chip_id, ct, nx842_ct);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void nx842_delete_coprocs(void)
|
|
{
|
|
struct nx842_coproc *coproc, *n;
|
|
struct vas_window *txwin;
|
|
int i;
|
|
|
|
/*
|
|
* close percpu txwins that are opened for the corresponding coproc.
|
|
*/
|
|
for_each_possible_cpu(i) {
|
|
txwin = per_cpu(cpu_txwin, i);
|
|
if (txwin)
|
|
vas_win_close(txwin);
|
|
|
|
per_cpu(cpu_txwin, i) = 0;
|
|
}
|
|
|
|
list_for_each_entry_safe(coproc, n, &nx842_coprocs, list) {
|
|
if (coproc->vas.rxwin)
|
|
vas_win_close(coproc->vas.rxwin);
|
|
|
|
list_del(&coproc->list);
|
|
kfree(coproc);
|
|
}
|
|
}
|
|
|
|
static struct nx842_constraints nx842_powernv_constraints = {
|
|
.alignment = DDE_BUFFER_ALIGN,
|
|
.multiple = DDE_BUFFER_LAST_MULT,
|
|
.minimum = DDE_BUFFER_LAST_MULT,
|
|
.maximum = (DDL_LEN_MAX - 1) * PAGE_SIZE,
|
|
};
|
|
|
|
static struct nx842_driver nx842_powernv_driver = {
|
|
.name = KBUILD_MODNAME,
|
|
.owner = THIS_MODULE,
|
|
.workmem_size = sizeof(struct nx842_workmem),
|
|
.constraints = &nx842_powernv_constraints,
|
|
.compress = nx842_powernv_compress,
|
|
.decompress = nx842_powernv_decompress,
|
|
};
|
|
|
|
static int nx842_powernv_crypto_init(struct crypto_tfm *tfm)
|
|
{
|
|
return nx842_crypto_init(tfm, &nx842_powernv_driver);
|
|
}
|
|
|
|
static struct crypto_alg nx842_powernv_alg = {
|
|
.cra_name = "842",
|
|
.cra_driver_name = "842-nx",
|
|
.cra_priority = 300,
|
|
.cra_flags = CRYPTO_ALG_TYPE_COMPRESS,
|
|
.cra_ctxsize = sizeof(struct nx842_crypto_ctx),
|
|
.cra_module = THIS_MODULE,
|
|
.cra_init = nx842_powernv_crypto_init,
|
|
.cra_exit = nx842_crypto_exit,
|
|
.cra_u = { .compress = {
|
|
.coa_compress = nx842_crypto_compress,
|
|
.coa_decompress = nx842_crypto_decompress } }
|
|
};
|
|
|
|
static __init int nx842_powernv_init(void)
|
|
{
|
|
struct device_node *dn;
|
|
int ret;
|
|
|
|
/* verify workmem size/align restrictions */
|
|
BUILD_BUG_ON(WORKMEM_ALIGN % CRB_ALIGN);
|
|
BUILD_BUG_ON(CRB_ALIGN % DDE_ALIGN);
|
|
BUILD_BUG_ON(CRB_SIZE % DDE_ALIGN);
|
|
/* verify buffer size/align restrictions */
|
|
BUILD_BUG_ON(PAGE_SIZE % DDE_BUFFER_ALIGN);
|
|
BUILD_BUG_ON(DDE_BUFFER_ALIGN % DDE_BUFFER_SIZE_MULT);
|
|
BUILD_BUG_ON(DDE_BUFFER_SIZE_MULT % DDE_BUFFER_LAST_MULT);
|
|
|
|
for_each_compatible_node(dn, NULL, "ibm,power9-nx") {
|
|
ret = nx842_powernv_probe_vas(dn);
|
|
if (ret) {
|
|
nx842_delete_coprocs();
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
if (list_empty(&nx842_coprocs)) {
|
|
for_each_compatible_node(dn, NULL, "ibm,power-nx")
|
|
nx842_powernv_probe(dn);
|
|
|
|
if (!nx842_ct)
|
|
return -ENODEV;
|
|
|
|
nx842_powernv_exec = nx842_exec_icswx;
|
|
} else {
|
|
ret = nx842_open_percpu_txwins();
|
|
if (ret) {
|
|
nx842_delete_coprocs();
|
|
return ret;
|
|
}
|
|
|
|
nx842_powernv_exec = nx842_exec_vas;
|
|
}
|
|
|
|
ret = crypto_register_alg(&nx842_powernv_alg);
|
|
if (ret) {
|
|
nx842_delete_coprocs();
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
module_init(nx842_powernv_init);
|
|
|
|
static void __exit nx842_powernv_exit(void)
|
|
{
|
|
crypto_unregister_alg(&nx842_powernv_alg);
|
|
|
|
nx842_delete_coprocs();
|
|
}
|
|
module_exit(nx842_powernv_exit);
|