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5f97f7f940
This adds support for the Atmel AVR32 architecture as well as the AT32AP7000 CPU and the AT32STK1000 development board. AVR32 is a new high-performance 32-bit RISC microprocessor core, designed for cost-sensitive embedded applications, with particular emphasis on low power consumption and high code density. The AVR32 architecture is not binary compatible with earlier 8-bit AVR architectures. The AVR32 architecture, including the instruction set, is described by the AVR32 Architecture Manual, available from http://www.atmel.com/dyn/resources/prod_documents/doc32000.pdf The Atmel AT32AP7000 is the first CPU implementing the AVR32 architecture. It features a 7-stage pipeline, 16KB instruction and data caches and a full Memory Management Unit. It also comes with a large set of integrated peripherals, many of which are shared with the AT91 ARM-based controllers from Atmel. Full data sheet is available from http://www.atmel.com/dyn/resources/prod_documents/doc32003.pdf while the CPU core implementation including caches and MMU is documented by the AVR32 AP Technical Reference, available from http://www.atmel.com/dyn/resources/prod_documents/doc32001.pdf Information about the AT32STK1000 development board can be found at http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3918 including a BSP CD image with an earlier version of this patch, development tools (binaries and source/patches) and a root filesystem image suitable for booting from SD card. Alternatively, there's a preliminary "getting started" guide available at http://avr32linux.org/twiki/bin/view/Main/GettingStarted which provides links to the sources and patches you will need in order to set up a cross-compiling environment for avr32-linux. This patch, as well as the other patches included with the BSP and the toolchain patches, is actively supported by Atmel Corporation. [dmccr@us.ibm.com: Fix more pxx_page macro locations] [bunk@stusta.de: fix `make defconfig'] Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com> Signed-off-by: Adrian Bunk <bunk@stusta.de> Signed-off-by: Dave McCracken <dmccr@us.ibm.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
129 lines
3.3 KiB
C
129 lines
3.3 KiB
C
#ifndef __ASM_AVR32_INTC_H
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#define __ASM_AVR32_INTC_H
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#include <linux/sysdev.h>
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#include <linux/interrupt.h>
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struct irq_controller;
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struct irqaction;
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struct pt_regs;
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struct platform_device;
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/* Information about the internal interrupt controller */
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struct intc_device {
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/* ioremapped address of configuration block */
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void __iomem *regs;
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/* the physical device */
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struct platform_device *pdev;
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/* Number of interrupt lines per group. */
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unsigned int irqs_per_group;
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/* The highest group ID + 1 */
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unsigned int nr_groups;
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/*
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* Bitfield indicating which groups are actually in use. The
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* size of the array is
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* ceil(group_max / (8 * sizeof(unsigned int))).
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*/
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unsigned int group_mask[];
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};
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struct irq_controller_class {
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/*
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* A short name identifying this kind of controller.
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*/
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const char *typename;
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/*
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* Handle the IRQ. Must do any necessary acking and masking.
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*/
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irqreturn_t (*handle)(int irq, void *dev_id, struct pt_regs *regs);
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/*
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* Register a new IRQ handler.
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*/
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int (*setup)(struct irq_controller *ctrl, unsigned int irq,
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struct irqaction *action);
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/*
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* Unregister a IRQ handler.
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*/
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void (*free)(struct irq_controller *ctrl, unsigned int irq,
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void *dev_id);
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/*
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* Mask the IRQ in the interrupt controller.
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*/
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void (*mask)(struct irq_controller *ctrl, unsigned int irq);
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/*
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* Unmask the IRQ in the interrupt controller.
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*/
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void (*unmask)(struct irq_controller *ctrl, unsigned int irq);
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/*
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* Set the type of the IRQ. See below for possible types.
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* Return -EINVAL if a given type is not supported
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*/
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int (*set_type)(struct irq_controller *ctrl, unsigned int irq,
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unsigned int type);
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/*
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* Return the IRQ type currently set
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*/
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unsigned int (*get_type)(struct irq_controller *ctrl, unsigned int irq);
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};
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struct irq_controller {
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struct irq_controller_class *class;
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unsigned int irq_group;
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unsigned int first_irq;
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unsigned int nr_irqs;
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struct list_head list;
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};
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struct intc_group_desc {
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struct irq_controller *ctrl;
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irqreturn_t (*handle)(int, void *, struct pt_regs *);
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unsigned long flags;
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void *dev_id;
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const char *devname;
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};
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/*
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* The internal interrupt controller. Defined in board/part-specific
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* devices.c.
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* TODO: Should probably be defined per-cpu.
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*/
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extern struct intc_device intc;
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extern int request_internal_irq(unsigned int irq,
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irqreturn_t (*handler)(int, void *, struct pt_regs *),
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unsigned long irqflags,
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const char *devname, void *dev_id);
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extern void free_internal_irq(unsigned int irq);
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/* Only used by time_init() */
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extern int setup_internal_irq(unsigned int irq, struct intc_group_desc *desc);
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/*
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* Set interrupt priority for a given group. `group' can be found by
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* using irq_to_group(irq). Priority can be from 0 (lowest) to 3
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* (highest). Higher-priority interrupts will preempt lower-priority
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* interrupts (unless interrupts are masked globally).
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*
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* This function does not check for conflicts within a group.
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*/
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extern int intc_set_priority(unsigned int group,
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unsigned int priority);
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/*
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* Returns a bitmask of pending interrupts in a group.
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*/
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extern unsigned long intc_get_pending(unsigned int group);
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/*
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* Register a new external interrupt controller. Returns the first
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* external IRQ number that is assigned to the new controller.
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*/
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extern int intc_register_controller(struct irq_controller *ctrl);
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#endif /* __ASM_AVR32_INTC_H */
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