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Documentation for IMC (In-Memory Collection Counters) infrastructure and trace-mode of IMC. Signed-off-by: Anju T Sudhakar <anju@linux.vnet.ibm.com> [mpe: Convert to rst, minor rewording, make PMI example more concise] Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20191028100816.6270-1-mpe@ellerman.id.au
200 lines
6.3 KiB
ReStructuredText
200 lines
6.3 KiB
ReStructuredText
.. SPDX-License-Identifier: GPL-2.0
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.. _imc:
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===================================
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IMC (In-Memory Collection Counters)
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===================================
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Anju T Sudhakar, 10 May 2019
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.. contents::
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:depth: 3
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Basic overview
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==============
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IMC (In-Memory collection counters) is a hardware monitoring facility that
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collects large numbers of hardware performance events at Nest level (these are
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on-chip but off-core), Core level and Thread level.
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The Nest PMU counters are handled by a Nest IMC microcode which runs in the OCC
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(On-Chip Controller) complex. The microcode collects the counter data and moves
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the nest IMC counter data to memory.
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The Core and Thread IMC PMU counters are handled in the core. Core level PMU
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counters give us the IMC counters' data per core and thread level PMU counters
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give us the IMC counters' data per CPU thread.
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OPAL obtains the IMC PMU and supported events information from the IMC Catalog
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and passes on to the kernel via the device tree. The event's information
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contains:
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- Event name
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- Event Offset
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- Event description
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and possibly also:
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- Event scale
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- Event unit
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Some PMUs may have a common scale and unit values for all their supported
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events. For those cases, the scale and unit properties for those events must be
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inherited from the PMU.
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The event offset in the memory is where the counter data gets accumulated.
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IMC catalog is available at:
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https://github.com/open-power/ima-catalog
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The kernel discovers the IMC counters information in the device tree at the
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`imc-counters` device node which has a compatible field
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`ibm,opal-in-memory-counters`. From the device tree, the kernel parses the PMUs
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and their event's information and register the PMU and its attributes in the
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kernel.
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IMC example usage
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=================
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.. code-block:: sh
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# perf list
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[...]
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nest_mcs01/PM_MCS01_64B_RD_DISP_PORT01/ [Kernel PMU event]
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nest_mcs01/PM_MCS01_64B_RD_DISP_PORT23/ [Kernel PMU event]
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[...]
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core_imc/CPM_0THRD_NON_IDLE_PCYC/ [Kernel PMU event]
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core_imc/CPM_1THRD_NON_IDLE_INST/ [Kernel PMU event]
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[...]
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thread_imc/CPM_0THRD_NON_IDLE_PCYC/ [Kernel PMU event]
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thread_imc/CPM_1THRD_NON_IDLE_INST/ [Kernel PMU event]
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To see per chip data for nest_mcs0/PM_MCS_DOWN_128B_DATA_XFER_MC0/:
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.. code-block:: sh
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# ./perf stat -e "nest_mcs01/PM_MCS01_64B_WR_DISP_PORT01/" -a --per-socket
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To see non-idle instructions for core 0:
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.. code-block:: sh
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# ./perf stat -e "core_imc/CPM_NON_IDLE_INST/" -C 0 -I 1000
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To see non-idle instructions for a "make":
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.. code-block:: sh
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# ./perf stat -e "thread_imc/CPM_NON_IDLE_PCYC/" make
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IMC Trace-mode
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===============
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POWER9 supports two modes for IMC which are the Accumulation mode and Trace
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mode. In Accumulation mode, event counts are accumulated in system Memory.
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Hypervisor then reads the posted counts periodically or when requested. In IMC
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Trace mode, the 64 bit trace SCOM value is initialized with the event
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information. The CPMCxSEL and CPMC_LOAD in the trace SCOM, specifies the event
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to be monitored and the sampling duration. On each overflow in the CPMCxSEL,
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hardware snapshots the program counter along with event counts and writes into
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memory pointed by LDBAR.
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LDBAR is a 64 bit special purpose per thread register, it has bits to indicate
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whether hardware is configured for accumulation or trace mode.
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LDBAR Register Layout
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---------------------
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+-------+----------------------+
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| 0 | Enable/Disable |
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+-------+----------------------+
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| 1 | 0: Accumulation Mode |
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| +----------------------+
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| | 1: Trace Mode |
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+-------+----------------------+
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| 2:3 | Reserved |
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+-------+----------------------+
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| 4-6 | PB scope |
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+-------+----------------------+
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| 7 | Reserved |
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+-------+----------------------+
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| 8:50 | Counter Address |
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+-------+----------------------+
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| 51:63 | Reserved |
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+-------+----------------------+
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TRACE_IMC_SCOM bit representation
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---------------------------------
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+-------+------------+
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| 0:1 | SAMPSEL |
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+-------+------------+
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| 2:33 | CPMC_LOAD |
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+-------+------------+
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| 34:40 | CPMC1SEL |
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+-------+------------+
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| 41:47 | CPMC2SEL |
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+-------+------------+
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| 48:50 | BUFFERSIZE |
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+-------+------------+
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| 51:63 | RESERVED |
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+-------+------------+
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CPMC_LOAD contains the sampling duration. SAMPSEL and CPMCxSEL determines the
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event to count. BUFFERSIZE indicates the memory range. On each overflow,
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hardware snapshots the program counter along with event counts and updates the
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memory and reloads the CMPC_LOAD value for the next sampling duration. IMC
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hardware does not support exceptions, so it quietly wraps around if memory
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buffer reaches the end.
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*Currently the event monitored for trace-mode is fixed as cycle.*
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Trace IMC example usage
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=======================
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.. code-block:: sh
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# perf list
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[....]
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trace_imc/trace_cycles/ [Kernel PMU event]
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To record an application/process with trace-imc event:
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.. code-block:: sh
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# perf record -e trace_imc/trace_cycles/ yes > /dev/null
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[ perf record: Woken up 1 times to write data ]
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[ perf record: Captured and wrote 0.012 MB perf.data (21 samples) ]
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The `perf.data` generated, can be read using perf report.
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Benefits of using IMC trace-mode
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================================
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PMI (Performance Monitoring Interrupts) interrupt handling is avoided, since IMC
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trace mode snapshots the program counter and updates to the memory. And this
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also provide a way for the operating system to do instruction sampling in real
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time without PMI processing overhead.
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Performance data using `perf top` with and without trace-imc event.
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PMI interrupts count when `perf top` command is executed without trace-imc event.
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.. code-block:: sh
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# grep PMI /proc/interrupts
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PMI: 0 0 0 0 Performance monitoring interrupts
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# ./perf top
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...
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# grep PMI /proc/interrupts
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PMI: 39735 8710 17338 17801 Performance monitoring interrupts
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# ./perf top -e trace_imc/trace_cycles/
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...
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# grep PMI /proc/interrupts
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PMI: 39735 8710 17338 17801 Performance monitoring interrupts
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That is, the PMI interrupt counts do not increment when using the `trace_imc` event.
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