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The pin controller has been updated in the Amlogic Meson AXG series, which use continuous 4-bit register to select function for each pin. In order to support this, a new pinmux operations "meson_axg_pmx_ops" has been added. Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> Reviewed-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
119 lines
3.0 KiB
C
119 lines
3.0 KiB
C
/*
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* Second generation of pinmux driver for Amlogic Meson-AXG SoC.
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*
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* Copyright (c) 2017 Baylibre SAS.
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* Author: Jerome Brunet <jbrunet@baylibre.com>
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*
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* Copyright (c) 2017 Amlogic, Inc. All rights reserved.
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* Author: Xingyu Chen <xingyu.chen@amlogic.com>
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*
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* SPDX-License-Identifier: (GPL-2.0+ or MIT)
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*/
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/*
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* This new generation of pinctrl IP is mainly adopted by the
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* Meson-AXG SoC and later series, which use 4-width continuous
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* register bit to select the function for each pin.
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*
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* The value 0 is always selecting the GPIO mode, while other
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* values (start from 1) for selecting the function mode.
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*/
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#include <linux/device.h>
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#include <linux/regmap.h>
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#include <linux/pinctrl/pinctrl.h>
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#include <linux/pinctrl/pinmux.h>
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#include "pinctrl-meson.h"
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#include "pinctrl-meson-axg-pmx.h"
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static int meson_axg_pmx_get_bank(struct meson_pinctrl *pc,
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unsigned int pin,
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struct meson_pmx_bank **bank)
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{
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int i;
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struct meson_axg_pmx_data *pmx = pc->data->pmx_data;
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for (i = 0; i < pmx->num_pmx_banks; i++)
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if (pin >= pmx->pmx_banks[i].first &&
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pin <= pmx->pmx_banks[i].last) {
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*bank = &pmx->pmx_banks[i];
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return 0;
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}
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return -EINVAL;
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}
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static int meson_pmx_calc_reg_and_offset(struct meson_pmx_bank *bank,
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unsigned int pin, unsigned int *reg,
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unsigned int *offset)
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{
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int shift;
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shift = pin - bank->first;
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*reg = bank->reg + (bank->offset + (shift << 2)) / 32;
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*offset = (bank->offset + (shift << 2)) % 32;
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return 0;
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}
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static int meson_axg_pmx_update_function(struct meson_pinctrl *pc,
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unsigned int pin, unsigned int func)
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{
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int ret;
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int reg;
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int offset;
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struct meson_pmx_bank *bank;
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ret = meson_axg_pmx_get_bank(pc, pin, &bank);
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if (ret)
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return ret;
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meson_pmx_calc_reg_and_offset(bank, pin, ®, &offset);
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ret = regmap_update_bits(pc->reg_mux, reg << 2,
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0xf << offset, (func & 0xf) << offset);
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return ret;
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}
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static int meson_axg_pmx_set_mux(struct pinctrl_dev *pcdev,
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unsigned int func_num, unsigned int group_num)
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{
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int i;
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int ret;
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struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
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struct meson_pmx_func *func = &pc->data->funcs[func_num];
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struct meson_pmx_group *group = &pc->data->groups[group_num];
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struct meson_pmx_axg_data *pmx_data =
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(struct meson_pmx_axg_data *)group->data;
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dev_dbg(pc->dev, "enable function %s, group %s\n", func->name,
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group->name);
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for (i = 0; i < group->num_pins; i++) {
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ret = meson_axg_pmx_update_function(pc, group->pins[i],
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pmx_data->func);
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if (ret)
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return ret;
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}
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return 0;
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}
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static int meson_axg_pmx_request_gpio(struct pinctrl_dev *pcdev,
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struct pinctrl_gpio_range *range, unsigned int offset)
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{
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struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
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return meson_axg_pmx_update_function(pc, offset, 0);
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}
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const struct pinmux_ops meson_axg_pmx_ops = {
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.set_mux = meson_axg_pmx_set_mux,
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.get_functions_count = meson_pmx_get_funcs_count,
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.get_function_name = meson_pmx_get_func_name,
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.get_function_groups = meson_pmx_get_groups,
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.gpio_request_enable = meson_axg_pmx_request_gpio,
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};
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