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4348810a24
Kernel space needs very little in the way of BTC maintanence as most mappings which are created and destroyed are non-executable, and so could never enter the instruction stream. The case which does warrant BTC maintanence is when a module is loaded. This creates a new executable mapping, but at that point the pages have not been initialized with code and data, so at that point they contain unpredictable information. Invalidating the BTC at this stage serves little useful purpose. Before we execute module code, we call flush_icache_range(), which deals with the BTC maintanence requirements. This ensures that we have a BTC maintanence operation before we execute code via the newly created mapping. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
89 lines
2.3 KiB
ArmAsm
89 lines
2.3 KiB
ArmAsm
/*
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* linux/arch/arm/mm/tlb-v7.S
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*
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* Copyright (C) 1997-2002 Russell King
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* Modified for ARMv7 by Catalin Marinas
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* ARM architecture version 6 TLB handling functions.
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* These assume a split I/D TLB.
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*/
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#include <linux/init.h>
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <asm/asm-offsets.h>
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#include <asm/page.h>
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#include <asm/tlbflush.h>
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#include "proc-macros.S"
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/*
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* v7wbi_flush_user_tlb_range(start, end, vma)
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*
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* Invalidate a range of TLB entries in the specified address space.
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*
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* - start - start address (may not be aligned)
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* - end - end address (exclusive, may not be aligned)
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* - vma - vma_struct describing address range
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*
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* It is assumed that:
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* - the "Invalidate single entry" instruction will invalidate
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* both the I and the D TLBs on Harvard-style TLBs
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*/
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ENTRY(v7wbi_flush_user_tlb_range)
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vma_vm_mm r3, r2 @ get vma->vm_mm
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mmid r3, r3 @ get vm_mm->context.id
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dsb
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mov r0, r0, lsr #PAGE_SHIFT @ align address
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mov r1, r1, lsr #PAGE_SHIFT
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asid r3, r3 @ mask ASID
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orr r0, r3, r0, lsl #PAGE_SHIFT @ Create initial MVA
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mov r1, r1, lsl #PAGE_SHIFT
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1:
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ALT_SMP(mcr p15, 0, r0, c8, c3, 1) @ TLB invalidate U MVA (shareable)
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ALT_UP(mcr p15, 0, r0, c8, c7, 1) @ TLB invalidate U MVA
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add r0, r0, #PAGE_SZ
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cmp r0, r1
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blo 1b
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dsb
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mov pc, lr
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ENDPROC(v7wbi_flush_user_tlb_range)
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/*
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* v7wbi_flush_kern_tlb_range(start,end)
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*
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* Invalidate a range of kernel TLB entries
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*
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* - start - start address (may not be aligned)
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* - end - end address (exclusive, may not be aligned)
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*/
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ENTRY(v7wbi_flush_kern_tlb_range)
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dsb
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mov r0, r0, lsr #PAGE_SHIFT @ align address
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mov r1, r1, lsr #PAGE_SHIFT
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mov r0, r0, lsl #PAGE_SHIFT
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mov r1, r1, lsl #PAGE_SHIFT
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1:
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ALT_SMP(mcr p15, 0, r0, c8, c3, 1) @ TLB invalidate U MVA (shareable)
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ALT_UP(mcr p15, 0, r0, c8, c7, 1) @ TLB invalidate U MVA
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add r0, r0, #PAGE_SZ
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cmp r0, r1
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blo 1b
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dsb
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isb
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mov pc, lr
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ENDPROC(v7wbi_flush_kern_tlb_range)
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__INIT
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.type v7wbi_tlb_fns, #object
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ENTRY(v7wbi_tlb_fns)
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.long v7wbi_flush_user_tlb_range
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.long v7wbi_flush_kern_tlb_range
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ALT_SMP(.long v7wbi_tlb_flags_smp)
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ALT_UP(.long v7wbi_tlb_flags_up)
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.size v7wbi_tlb_fns, . - v7wbi_tlb_fns
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