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a982e45dc1
When a USB device is connected to the USB host port on the SAM9N12 then you get "-62" error which seems to indicate USB replies from the device are timing out. Based on a logic sniffer, I saw the USB bus was running at half speed. The PLL code uses cached MUL and DIV values which get set in set_rate() and applied in prepare(), but the recalc_rate() function instead queries the hardware instead of using these cached values. Therefore, if recalc_rate() is called between a set_rate() and prepare(), the wrong frequency is calculated and later the USB clock divider for the SAM9N12 SOC will be configured for an incorrect clock. In my case, the PLL hardware was set to 96 Mhz before the OHCI driver loads, and therefore the usb clock divider was being set to /2 even though the OHCI driver set the PLL to 48 Mhz. As an alternative explanation, I noticed this was fixed in the past by |
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| .. | ||
| clk-audio-pll.c | ||
| clk-generated.c | ||
| clk-h32mx.c | ||
| clk-main.c | ||
| clk-master.c | ||
| clk-peripheral.c | ||
| clk-pll.c | ||
| clk-plldiv.c | ||
| clk-programmable.c | ||
| clk-slow.c | ||
| clk-smd.c | ||
| clk-system.c | ||
| clk-usb.c | ||
| clk-utmi.c | ||
| Makefile | ||
| pmc.c | ||
| pmc.h | ||
| sckc.c | ||