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6ab3d5624e
Signed-off-by: Jörn Engel <joern@wohnheim.fh-wedel.de> Signed-off-by: Adrian Bunk <bunk@stusta.de>
100 lines
2.6 KiB
ArmAsm
100 lines
2.6 KiB
ArmAsm
/* atomic.S: Move this stuff here for better ICACHE hit rates.
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*
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* Copyright (C) 1996 David S. Miller (davem@caipfs.rutgers.edu)
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*/
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#include <asm/ptrace.h>
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#include <asm/psr.h>
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.text
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.align 4
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.globl __atomic_begin
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__atomic_begin:
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#ifndef CONFIG_SMP
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.globl ___xchg32_sun4c
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___xchg32_sun4c:
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rd %psr, %g3
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andcc %g3, PSR_PIL, %g0
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bne 1f
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nop
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wr %g3, PSR_PIL, %psr
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nop; nop; nop
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1:
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andcc %g3, PSR_PIL, %g0
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ld [%g1], %g7
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bne 1f
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st %g2, [%g1]
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wr %g3, 0x0, %psr
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nop; nop; nop
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1:
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mov %g7, %g2
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jmpl %o7 + 8, %g0
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mov %g4, %o7
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.globl ___xchg32_sun4md
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___xchg32_sun4md:
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swap [%g1], %g2
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jmpl %o7 + 8, %g0
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mov %g4, %o7
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#endif
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/* Read asm-sparc/atomic.h carefully to understand how this works for SMP.
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* Really, some things here for SMP are overly clever, go read the header.
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*/
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.globl ___atomic24_add
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___atomic24_add:
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rd %psr, %g3 ! Keep the code small, old way was stupid
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nop; nop; nop; ! Let the bits set
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or %g3, PSR_PIL, %g7 ! Disable interrupts
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wr %g7, 0x0, %psr ! Set %psr
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nop; nop; nop; ! Let the bits set
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#ifdef CONFIG_SMP
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1: ldstub [%g1 + 3], %g7 ! Spin on the byte lock for SMP.
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orcc %g7, 0x0, %g0 ! Did we get it?
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bne 1b ! Nope...
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ld [%g1], %g7 ! Load locked atomic24_t
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sra %g7, 8, %g7 ! Get signed 24-bit integer
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add %g7, %g2, %g2 ! Add in argument
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sll %g2, 8, %g7 ! Transpose back to atomic24_t
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st %g7, [%g1] ! Clever: This releases the lock as well.
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#else
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ld [%g1], %g7 ! Load locked atomic24_t
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add %g7, %g2, %g2 ! Add in argument
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st %g2, [%g1] ! Store it back
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#endif
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wr %g3, 0x0, %psr ! Restore original PSR_PIL
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nop; nop; nop; ! Let the bits set
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jmpl %o7, %g0 ! NOTE: not + 8, see callers in atomic.h
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mov %g4, %o7 ! Restore %o7
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.globl ___atomic24_sub
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___atomic24_sub:
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rd %psr, %g3 ! Keep the code small, old way was stupid
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nop; nop; nop; ! Let the bits set
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or %g3, PSR_PIL, %g7 ! Disable interrupts
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wr %g7, 0x0, %psr ! Set %psr
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nop; nop; nop; ! Let the bits set
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#ifdef CONFIG_SMP
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1: ldstub [%g1 + 3], %g7 ! Spin on the byte lock for SMP.
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orcc %g7, 0x0, %g0 ! Did we get it?
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bne 1b ! Nope...
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ld [%g1], %g7 ! Load locked atomic24_t
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sra %g7, 8, %g7 ! Get signed 24-bit integer
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sub %g7, %g2, %g2 ! Subtract argument
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sll %g2, 8, %g7 ! Transpose back to atomic24_t
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st %g7, [%g1] ! Clever: This releases the lock as well
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#else
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ld [%g1], %g7 ! Load locked atomic24_t
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sub %g7, %g2, %g2 ! Subtract argument
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st %g2, [%g1] ! Store it back
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#endif
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wr %g3, 0x0, %psr ! Restore original PSR_PIL
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nop; nop; nop; ! Let the bits set
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jmpl %o7, %g0 ! NOTE: not + 8, see callers in atomic.h
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mov %g4, %o7 ! Restore %o7
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.globl __atomic_end
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__atomic_end:
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