mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-22 20:23:57 +08:00
d70f82acf3
Pass symbol-prefix to genksyms instead of arch, so that the decision what symbol prefix to use is kept in one place. Basically genksyms used to take a -a $ARCH argument and it used that to determine whether to add an underscore symbol prefix. It's now changed to take a -s $SYMBOL_PREFIX argument so that the caller decides whether a symbol prefix is required. The build system then uses CONFIG_HAVE_UNDERSCORE_SYMBOL_PREFIX to determine whether to pass the argument. Signed-off-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: Rusty Russell <rusty@rustcorp.com.au>
480 lines
15 KiB
Makefile
480 lines
15 KiB
Makefile
# ==========================================================================
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# Building
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# ==========================================================================
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src := $(obj)
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PHONY := __build
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__build:
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# Init all relevant variables used in kbuild files so
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# 1) they have correct type
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# 2) they do not inherit any value from the environment
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obj-y :=
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obj-m :=
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lib-y :=
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lib-m :=
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always :=
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targets :=
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subdir-y :=
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subdir-m :=
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EXTRA_AFLAGS :=
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EXTRA_CFLAGS :=
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EXTRA_CPPFLAGS :=
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EXTRA_LDFLAGS :=
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asflags-y :=
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ccflags-y :=
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cppflags-y :=
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ldflags-y :=
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subdir-asflags-y :=
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subdir-ccflags-y :=
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# Read auto.conf if it exists, otherwise ignore
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-include include/config/auto.conf
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include scripts/Kbuild.include
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# For backward compatibility check that these variables do not change
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save-cflags := $(CFLAGS)
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# The filename Kbuild has precedence over Makefile
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kbuild-dir := $(if $(filter /%,$(src)),$(src),$(srctree)/$(src))
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kbuild-file := $(if $(wildcard $(kbuild-dir)/Kbuild),$(kbuild-dir)/Kbuild,$(kbuild-dir)/Makefile)
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include $(kbuild-file)
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# If the save-* variables changed error out
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ifeq ($(KBUILD_NOPEDANTIC),)
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ifneq ("$(save-cflags)","$(CFLAGS)")
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$(error CFLAGS was changed in "$(kbuild-file)". Fix it to use ccflags-y)
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endif
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endif
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#
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# make W=... settings
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#
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# W=1 - warnings that may be relevant and does not occur too often
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# W=2 - warnings that occur quite often but may still be relevant
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# W=3 - the more obscure warnings, can most likely be ignored
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#
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# $(call cc-option, -W...) handles gcc -W.. options which
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# are not supported by all versions of the compiler
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ifdef KBUILD_ENABLE_EXTRA_GCC_CHECKS
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warning- := $(empty)
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warning-1 := -Wextra -Wunused -Wno-unused-parameter
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warning-1 += -Wmissing-declarations
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warning-1 += -Wmissing-format-attribute
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warning-1 += -Wmissing-prototypes
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warning-1 += -Wold-style-definition
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warning-1 += $(call cc-option, -Wmissing-include-dirs)
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warning-1 += $(call cc-option, -Wunused-but-set-variable)
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warning-1 += $(call cc-disable-warning, missing-field-initializers)
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warning-2 := -Waggregate-return
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warning-2 += -Wcast-align
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warning-2 += -Wdisabled-optimization
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warning-2 += -Wnested-externs
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warning-2 += -Wshadow
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warning-2 += $(call cc-option, -Wlogical-op)
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warning-2 += $(call cc-option, -Wmissing-field-initializers)
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warning-3 := -Wbad-function-cast
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warning-3 += -Wcast-qual
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warning-3 += -Wconversion
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warning-3 += -Wpacked
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warning-3 += -Wpadded
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warning-3 += -Wpointer-arith
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warning-3 += -Wredundant-decls
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warning-3 += -Wswitch-default
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warning-3 += $(call cc-option, -Wpacked-bitfield-compat)
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warning-3 += $(call cc-option, -Wvla)
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warning := $(warning-$(findstring 1, $(KBUILD_ENABLE_EXTRA_GCC_CHECKS)))
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warning += $(warning-$(findstring 2, $(KBUILD_ENABLE_EXTRA_GCC_CHECKS)))
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warning += $(warning-$(findstring 3, $(KBUILD_ENABLE_EXTRA_GCC_CHECKS)))
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ifeq ("$(strip $(warning))","")
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$(error W=$(KBUILD_ENABLE_EXTRA_GCC_CHECKS) is unknown)
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endif
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KBUILD_CFLAGS += $(warning)
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endif
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include scripts/Makefile.lib
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ifdef host-progs
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ifneq ($(hostprogs-y),$(host-progs))
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$(warning kbuild: $(obj)/Makefile - Usage of host-progs is deprecated. Please replace with hostprogs-y!)
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hostprogs-y += $(host-progs)
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endif
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endif
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# Do not include host rules unless needed
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ifneq ($(hostprogs-y)$(hostprogs-m),)
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include scripts/Makefile.host
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endif
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ifneq ($(KBUILD_SRC),)
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# Create output directory if not already present
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_dummy := $(shell [ -d $(obj) ] || mkdir -p $(obj))
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# Create directories for object files if directory does not exist
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# Needed when obj-y := dir/file.o syntax is used
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_dummy := $(foreach d,$(obj-dirs), $(shell [ -d $(d) ] || mkdir -p $(d)))
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endif
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ifndef obj
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$(warning kbuild: Makefile.build is included improperly)
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endif
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# ===========================================================================
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ifneq ($(strip $(lib-y) $(lib-m) $(lib-n) $(lib-)),)
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lib-target := $(obj)/lib.a
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endif
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ifneq ($(strip $(obj-y) $(obj-m) $(obj-n) $(obj-) $(subdir-m) $(lib-target)),)
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builtin-target := $(obj)/built-in.o
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endif
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modorder-target := $(obj)/modules.order
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# We keep a list of all modules in $(MODVERDIR)
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__build: $(if $(KBUILD_BUILTIN),$(builtin-target) $(lib-target) $(extra-y)) \
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$(if $(KBUILD_MODULES),$(obj-m) $(modorder-target)) \
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$(subdir-ym) $(always)
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@:
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# Linus' kernel sanity checking tool
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ifneq ($(KBUILD_CHECKSRC),0)
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ifeq ($(KBUILD_CHECKSRC),2)
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quiet_cmd_force_checksrc = CHECK $<
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cmd_force_checksrc = $(CHECK) $(CHECKFLAGS) $(c_flags) $< ;
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else
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quiet_cmd_checksrc = CHECK $<
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cmd_checksrc = $(CHECK) $(CHECKFLAGS) $(c_flags) $< ;
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endif
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endif
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# Do section mismatch analysis for each module/built-in.o
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ifdef CONFIG_DEBUG_SECTION_MISMATCH
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cmd_secanalysis = ; scripts/mod/modpost $@
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endif
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# Compile C sources (.c)
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# ---------------------------------------------------------------------------
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# Default is built-in, unless we know otherwise
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modkern_cflags = \
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$(if $(part-of-module), \
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$(KBUILD_CFLAGS_MODULE) $(CFLAGS_MODULE), \
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$(KBUILD_CFLAGS_KERNEL) $(CFLAGS_KERNEL))
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quiet_modtag := $(empty) $(empty)
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$(real-objs-m) : part-of-module := y
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$(real-objs-m:.o=.i) : part-of-module := y
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$(real-objs-m:.o=.s) : part-of-module := y
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$(real-objs-m:.o=.lst): part-of-module := y
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$(real-objs-m) : quiet_modtag := [M]
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$(real-objs-m:.o=.i) : quiet_modtag := [M]
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$(real-objs-m:.o=.s) : quiet_modtag := [M]
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$(real-objs-m:.o=.lst): quiet_modtag := [M]
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$(obj-m) : quiet_modtag := [M]
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# Default for not multi-part modules
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modname = $(basetarget)
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$(multi-objs-m) : modname = $(modname-multi)
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$(multi-objs-m:.o=.i) : modname = $(modname-multi)
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$(multi-objs-m:.o=.s) : modname = $(modname-multi)
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$(multi-objs-m:.o=.lst) : modname = $(modname-multi)
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$(multi-objs-y) : modname = $(modname-multi)
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$(multi-objs-y:.o=.i) : modname = $(modname-multi)
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$(multi-objs-y:.o=.s) : modname = $(modname-multi)
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$(multi-objs-y:.o=.lst) : modname = $(modname-multi)
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quiet_cmd_cc_s_c = CC $(quiet_modtag) $@
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cmd_cc_s_c = $(CC) $(c_flags) -fverbose-asm -S -o $@ $<
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$(obj)/%.s: $(src)/%.c FORCE
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$(call if_changed_dep,cc_s_c)
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quiet_cmd_cc_i_c = CPP $(quiet_modtag) $@
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cmd_cc_i_c = $(CPP) $(c_flags) -o $@ $<
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$(obj)/%.i: $(src)/%.c FORCE
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$(call if_changed_dep,cc_i_c)
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cmd_gensymtypes = \
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$(CPP) -D__GENKSYMS__ $(c_flags) $< | \
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$(GENKSYMS) $(if $(1), -T $(2)) \
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$(patsubst y,-s _,$(CONFIG_HAVE_UNDERSCORE_SYMBOL_PREFIX)) \
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$(if $(KBUILD_PRESERVE),-p) \
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-r $(firstword $(wildcard $(2:.symtypes=.symref) /dev/null))
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quiet_cmd_cc_symtypes_c = SYM $(quiet_modtag) $@
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cmd_cc_symtypes_c = \
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set -e; \
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$(call cmd_gensymtypes,true,$@) >/dev/null; \
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test -s $@ || rm -f $@
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$(obj)/%.symtypes : $(src)/%.c FORCE
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$(call cmd,cc_symtypes_c)
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# C (.c) files
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# The C file is compiled and updated dependency information is generated.
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# (See cmd_cc_o_c + relevant part of rule_cc_o_c)
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quiet_cmd_cc_o_c = CC $(quiet_modtag) $@
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ifndef CONFIG_MODVERSIONS
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cmd_cc_o_c = $(CC) $(c_flags) -c -o $@ $<
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else
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# When module versioning is enabled the following steps are executed:
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# o compile a .tmp_<file>.o from <file>.c
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# o if .tmp_<file>.o doesn't contain a __ksymtab version, i.e. does
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# not export symbols, we just rename .tmp_<file>.o to <file>.o and
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# are done.
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# o otherwise, we calculate symbol versions using the good old
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# genksyms on the preprocessed source and postprocess them in a way
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# that they are usable as a linker script
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# o generate <file>.o from .tmp_<file>.o using the linker to
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# replace the unresolved symbols __crc_exported_symbol with
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# the actual value of the checksum generated by genksyms
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cmd_cc_o_c = $(CC) $(c_flags) -c -o $(@D)/.tmp_$(@F) $<
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cmd_modversions = \
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if $(OBJDUMP) -h $(@D)/.tmp_$(@F) | grep -q __ksymtab; then \
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$(call cmd_gensymtypes,$(KBUILD_SYMTYPES),$(@:.o=.symtypes)) \
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> $(@D)/.tmp_$(@F:.o=.ver); \
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\
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$(LD) $(LDFLAGS) -r -o $@ $(@D)/.tmp_$(@F) \
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-T $(@D)/.tmp_$(@F:.o=.ver); \
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rm -f $(@D)/.tmp_$(@F) $(@D)/.tmp_$(@F:.o=.ver); \
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else \
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mv -f $(@D)/.tmp_$(@F) $@; \
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fi;
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endif
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ifdef CONFIG_FTRACE_MCOUNT_RECORD
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ifdef BUILD_C_RECORDMCOUNT
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ifeq ("$(origin RECORDMCOUNT_WARN)", "command line")
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RECORDMCOUNT_FLAGS = -w
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endif
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# Due to recursion, we must skip empty.o.
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# The empty.o file is created in the make process in order to determine
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# the target endianness and word size. It is made before all other C
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# files, including recordmcount.
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sub_cmd_record_mcount = \
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if [ $(@) != "scripts/mod/empty.o" ]; then \
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$(objtree)/scripts/recordmcount $(RECORDMCOUNT_FLAGS) "$(@)"; \
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fi;
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recordmcount_source := $(srctree)/scripts/recordmcount.c \
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$(srctree)/scripts/recordmcount.h
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else
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sub_cmd_record_mcount = set -e ; perl $(srctree)/scripts/recordmcount.pl "$(ARCH)" \
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"$(if $(CONFIG_CPU_BIG_ENDIAN),big,little)" \
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"$(if $(CONFIG_64BIT),64,32)" \
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"$(OBJDUMP)" "$(OBJCOPY)" "$(CC) $(KBUILD_CFLAGS)" \
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"$(LD)" "$(NM)" "$(RM)" "$(MV)" \
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"$(if $(part-of-module),1,0)" "$(@)";
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recordmcount_source := $(srctree)/scripts/recordmcount.pl
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endif
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cmd_record_mcount = \
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if [ "$(findstring -pg,$(_c_flags))" = "-pg" ]; then \
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$(sub_cmd_record_mcount) \
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fi;
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endif
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define rule_cc_o_c
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$(call echo-cmd,checksrc) $(cmd_checksrc) \
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$(call echo-cmd,cc_o_c) $(cmd_cc_o_c); \
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$(cmd_modversions) \
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$(call echo-cmd,record_mcount) \
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$(cmd_record_mcount) \
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scripts/basic/fixdep $(depfile) $@ '$(call make-cmd,cc_o_c)' > \
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$(dot-target).tmp; \
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rm -f $(depfile); \
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mv -f $(dot-target).tmp $(dot-target).cmd
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endef
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# Built-in and composite module parts
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$(obj)/%.o: $(src)/%.c $(recordmcount_source) FORCE
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$(call cmd,force_checksrc)
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$(call if_changed_rule,cc_o_c)
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# Single-part modules are special since we need to mark them in $(MODVERDIR)
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$(single-used-m): $(obj)/%.o: $(src)/%.c $(recordmcount_source) FORCE
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$(call cmd,force_checksrc)
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$(call if_changed_rule,cc_o_c)
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@{ echo $(@:.o=.ko); echo $@; } > $(MODVERDIR)/$(@F:.o=.mod)
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quiet_cmd_cc_lst_c = MKLST $@
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cmd_cc_lst_c = $(CC) $(c_flags) -g -c -o $*.o $< && \
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$(CONFIG_SHELL) $(srctree)/scripts/makelst $*.o \
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System.map $(OBJDUMP) > $@
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$(obj)/%.lst: $(src)/%.c FORCE
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$(call if_changed_dep,cc_lst_c)
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# Compile assembler sources (.S)
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# ---------------------------------------------------------------------------
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modkern_aflags := $(KBUILD_AFLAGS_KERNEL) $(AFLAGS_KERNEL)
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$(real-objs-m) : modkern_aflags := $(KBUILD_AFLAGS_MODULE) $(AFLAGS_MODULE)
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$(real-objs-m:.o=.s): modkern_aflags := $(KBUILD_AFLAGS_MODULE) $(AFLAGS_MODULE)
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quiet_cmd_as_s_S = CPP $(quiet_modtag) $@
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cmd_as_s_S = $(CPP) $(a_flags) -o $@ $<
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$(obj)/%.s: $(src)/%.S FORCE
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$(call if_changed_dep,as_s_S)
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quiet_cmd_as_o_S = AS $(quiet_modtag) $@
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cmd_as_o_S = $(CC) $(a_flags) -c -o $@ $<
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$(obj)/%.o: $(src)/%.S FORCE
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$(call if_changed_dep,as_o_S)
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targets += $(real-objs-y) $(real-objs-m) $(lib-y)
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targets += $(extra-y) $(MAKECMDGOALS) $(always)
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# Linker scripts preprocessor (.lds.S -> .lds)
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# ---------------------------------------------------------------------------
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quiet_cmd_cpp_lds_S = LDS $@
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cmd_cpp_lds_S = $(CPP) $(cpp_flags) -P -C -U$(ARCH) \
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-D__ASSEMBLY__ -DLINKER_SCRIPT -o $@ $<
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$(obj)/%.lds: $(src)/%.lds.S FORCE
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$(call if_changed_dep,cpp_lds_S)
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# ASN.1 grammar
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# ---------------------------------------------------------------------------
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quiet_cmd_asn1_compiler = ASN.1 $@
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cmd_asn1_compiler = $(objtree)/scripts/asn1_compiler $< \
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$(subst .h,.c,$@) $(subst .c,.h,$@)
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.PRECIOUS: $(objtree)/$(obj)/%-asn1.c $(objtree)/$(obj)/%-asn1.h
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$(obj)/%-asn1.c $(obj)/%-asn1.h: $(src)/%.asn1 $(objtree)/scripts/asn1_compiler
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$(call cmd,asn1_compiler)
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# Build the compiled-in targets
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# ---------------------------------------------------------------------------
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# To build objects in subdirs, we need to descend into the directories
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$(sort $(subdir-obj-y)): $(subdir-ym) ;
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#
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# Rule to compile a set of .o files into one .o file
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#
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ifdef builtin-target
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quiet_cmd_link_o_target = LD $@
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# If the list of objects to link is empty, just create an empty built-in.o
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cmd_link_o_target = $(if $(strip $(obj-y)),\
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$(LD) $(ld_flags) -r -o $@ $(filter $(obj-y), $^) \
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$(cmd_secanalysis),\
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rm -f $@; $(AR) rcs$(KBUILD_ARFLAGS) $@)
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$(builtin-target): $(obj-y) FORCE
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$(call if_changed,link_o_target)
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targets += $(builtin-target)
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endif # builtin-target
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#
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# Rule to create modules.order file
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#
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# Create commands to either record .ko file or cat modules.order from
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# a subdirectory
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modorder-cmds = \
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$(foreach m, $(modorder), \
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$(if $(filter %/modules.order, $m), \
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cat $m;, echo kernel/$m;))
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$(modorder-target): $(subdir-ym) FORCE
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$(Q)(cat /dev/null; $(modorder-cmds)) > $@
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#
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# Rule to compile a set of .o files into one .a file
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#
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ifdef lib-target
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quiet_cmd_link_l_target = AR $@
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cmd_link_l_target = rm -f $@; $(AR) rcs$(KBUILD_ARFLAGS) $@ $(lib-y)
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$(lib-target): $(lib-y) FORCE
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$(call if_changed,link_l_target)
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targets += $(lib-target)
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endif
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#
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# Rule to link composite objects
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#
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# Composite objects are specified in kbuild makefile as follows:
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# <composite-object>-objs := <list of .o files>
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# or
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# <composite-object>-y := <list of .o files>
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link_multi_deps = \
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$(filter $(addprefix $(obj)/, \
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$($(subst $(obj)/,,$(@:.o=-objs))) \
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$($(subst $(obj)/,,$(@:.o=-y)))), $^)
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quiet_cmd_link_multi-y = LD $@
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cmd_link_multi-y = $(LD) $(ld_flags) -r -o $@ $(link_multi_deps) $(cmd_secanalysis)
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quiet_cmd_link_multi-m = LD [M] $@
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cmd_link_multi-m = $(cmd_link_multi-y)
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# We would rather have a list of rules like
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# foo.o: $(foo-objs)
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# but that's not so easy, so we rather make all composite objects depend
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# on the set of all their parts
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$(multi-used-y) : %.o: $(multi-objs-y) FORCE
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$(call if_changed,link_multi-y)
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$(multi-used-m) : %.o: $(multi-objs-m) FORCE
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$(call if_changed,link_multi-m)
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@{ echo $(@:.o=.ko); echo $(link_multi_deps); } > $(MODVERDIR)/$(@F:.o=.mod)
|
|
|
|
targets += $(multi-used-y) $(multi-used-m)
|
|
|
|
|
|
# Descending
|
|
# ---------------------------------------------------------------------------
|
|
|
|
PHONY += $(subdir-ym)
|
|
$(subdir-ym):
|
|
$(Q)$(MAKE) $(build)=$@
|
|
|
|
# Add FORCE to the prequisites of a target to force it to be always rebuilt.
|
|
# ---------------------------------------------------------------------------
|
|
|
|
PHONY += FORCE
|
|
|
|
FORCE:
|
|
|
|
# Read all saved command lines and dependencies for the $(targets) we
|
|
# may be building above, using $(if_changed{,_dep}). As an
|
|
# optimization, we don't need to read them if the target does not
|
|
# exist, we will rebuild anyway in that case.
|
|
|
|
targets := $(wildcard $(sort $(targets)))
|
|
cmd_files := $(wildcard $(foreach f,$(targets),$(dir $(f)).$(notdir $(f)).cmd))
|
|
|
|
ifneq ($(cmd_files),)
|
|
include $(cmd_files)
|
|
endif
|
|
|
|
# Declare the contents of the .PHONY variable as phony. We keep that
|
|
# information in a variable se we can use it in if_changed and friends.
|
|
|
|
.PHONY: $(PHONY)
|