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f0774d41da
Add the necessary code to initialize the interrupt controller thru devicetree data using the irqchip infrastructure. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
54 lines
1.6 KiB
Plaintext
54 lines
1.6 KiB
Plaintext
Samsung S3C24XX Interrupt Controllers
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The S3C24XX SoCs contain a custom set of interrupt controllers providing a
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varying number of interrupt sources. The set consists of a main- and sub-
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controller and on newer SoCs even a second main controller.
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Required properties:
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- compatible: Compatible property value should be "samsung,s3c2410-irq"
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for machines before s3c2416 and "samsung,s3c2416-irq" for s3c2416 and later.
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- reg: Physical base address of the controller and length of memory mapped
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region.
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- interrupt-controller : Identifies the node as an interrupt controller
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- #interrupt-cells : Specifies the number of cells needed to encode an
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interrupt source. The value shall be 4 and interrupt descriptor shall
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have the following format:
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<ctrl_num parent_irq ctrl_irq type>
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ctrl_num contains the controller to use:
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- 0 ... main controller
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- 1 ... sub controller
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- 2 ... second main controller on s3c2416 and s3c2450
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parent_irq contains the parent bit in the main controller and will be
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ignored in main controllers
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ctrl_irq contains the interrupt bit of the controller
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type contains the trigger type to use
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Example:
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interrupt-controller@4a000000 {
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compatible = "samsung,s3c2410-irq";
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reg = <0x4a000000 0x100>;
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interrupt-controller;
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#interrupt-cells=<4>;
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};
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[...]
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serial@50000000 {
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compatible = "samsung,s3c2410-uart";
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reg = <0x50000000 0x4000>;
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interrupt-parent = <&subintc>;
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interrupts = <1 28 0 4>, <1 28 1 4>;
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};
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rtc@57000000 {
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compatible = "samsung,s3c2410-rtc";
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reg = <0x57000000 0x100>;
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interrupt-parent = <&intc>;
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interrupts = <0 30 0 3>, <0 8 0 3>;
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};
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