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240 lines
6.9 KiB
C
240 lines
6.9 KiB
C
/*
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* OMAP4 PRM module functions
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*
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* Copyright (C) 2011 Texas Instruments, Inc.
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* Copyright (C) 2010 Nokia Corporation
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* Benoît Cousson
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* Paul Walmsley
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/delay.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include "common.h"
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#include <plat/cpu.h>
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#include <plat/prcm.h>
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#include "vp.h"
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#include "prm44xx.h"
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#include "prm-regbits-44xx.h"
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#include "prcm44xx.h"
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#include "prminst44xx.h"
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static const struct omap_prcm_irq omap4_prcm_irqs[] = {
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OMAP_PRCM_IRQ("wkup", 0, 0),
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OMAP_PRCM_IRQ("io", 9, 1),
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};
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static struct omap_prcm_irq_setup omap4_prcm_irq_setup = {
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.ack = OMAP4_PRM_IRQSTATUS_MPU_OFFSET,
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.mask = OMAP4_PRM_IRQENABLE_MPU_OFFSET,
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.nr_regs = 2,
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.irqs = omap4_prcm_irqs,
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.nr_irqs = ARRAY_SIZE(omap4_prcm_irqs),
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.irq = OMAP44XX_IRQ_PRCM,
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.read_pending_irqs = &omap44xx_prm_read_pending_irqs,
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.ocp_barrier = &omap44xx_prm_ocp_barrier,
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.save_and_clear_irqen = &omap44xx_prm_save_and_clear_irqen,
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.restore_irqen = &omap44xx_prm_restore_irqen,
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};
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/* PRM low-level functions */
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/* Read a register in a CM/PRM instance in the PRM module */
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u32 omap4_prm_read_inst_reg(s16 inst, u16 reg)
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{
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return __raw_readl(OMAP44XX_PRM_REGADDR(inst, reg));
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}
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/* Write into a register in a CM/PRM instance in the PRM module */
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void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 reg)
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{
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__raw_writel(val, OMAP44XX_PRM_REGADDR(inst, reg));
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}
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/* Read-modify-write a register in a PRM module. Caller must lock */
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u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 reg)
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{
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u32 v;
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v = omap4_prm_read_inst_reg(inst, reg);
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v &= ~mask;
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v |= bits;
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omap4_prm_write_inst_reg(v, inst, reg);
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return v;
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}
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/* PRM VP */
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/*
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* struct omap4_vp - OMAP4 VP register access description.
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* @irqstatus_mpu: offset to IRQSTATUS_MPU register for VP
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* @tranxdone_status: VP_TRANXDONE_ST bitmask in PRM_IRQSTATUS_MPU reg
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*/
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struct omap4_vp {
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u32 irqstatus_mpu;
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u32 tranxdone_status;
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};
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static struct omap4_vp omap4_vp[] = {
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[OMAP4_VP_VDD_MPU_ID] = {
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.irqstatus_mpu = OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET,
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.tranxdone_status = OMAP4430_VP_MPU_TRANXDONE_ST_MASK,
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},
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[OMAP4_VP_VDD_IVA_ID] = {
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.irqstatus_mpu = OMAP4_PRM_IRQSTATUS_MPU_OFFSET,
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.tranxdone_status = OMAP4430_VP_IVA_TRANXDONE_ST_MASK,
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},
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[OMAP4_VP_VDD_CORE_ID] = {
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.irqstatus_mpu = OMAP4_PRM_IRQSTATUS_MPU_OFFSET,
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.tranxdone_status = OMAP4430_VP_CORE_TRANXDONE_ST_MASK,
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},
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};
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u32 omap4_prm_vp_check_txdone(u8 vp_id)
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{
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struct omap4_vp *vp = &omap4_vp[vp_id];
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u32 irqstatus;
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irqstatus = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
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OMAP4430_PRM_OCP_SOCKET_INST,
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vp->irqstatus_mpu);
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return irqstatus & vp->tranxdone_status;
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}
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void omap4_prm_vp_clear_txdone(u8 vp_id)
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{
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struct omap4_vp *vp = &omap4_vp[vp_id];
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omap4_prminst_write_inst_reg(vp->tranxdone_status,
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OMAP4430_PRM_PARTITION,
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OMAP4430_PRM_OCP_SOCKET_INST,
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vp->irqstatus_mpu);
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};
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u32 omap4_prm_vcvp_read(u8 offset)
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{
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return omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
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OMAP4430_PRM_DEVICE_INST, offset);
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}
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void omap4_prm_vcvp_write(u32 val, u8 offset)
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{
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omap4_prminst_write_inst_reg(val, OMAP4430_PRM_PARTITION,
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OMAP4430_PRM_DEVICE_INST, offset);
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}
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u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset)
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{
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return omap4_prminst_rmw_inst_reg_bits(mask, bits,
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OMAP4430_PRM_PARTITION,
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OMAP4430_PRM_DEVICE_INST,
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offset);
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}
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static inline u32 _read_pending_irq_reg(u16 irqen_offs, u16 irqst_offs)
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{
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u32 mask, st;
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/* XXX read mask from RAM? */
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mask = omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST, irqen_offs);
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st = omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST, irqst_offs);
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return mask & st;
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}
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/**
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* omap44xx_prm_read_pending_irqs - read pending PRM MPU IRQs into @events
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* @events: ptr to two consecutive u32s, preallocated by caller
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*
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* Read PRM_IRQSTATUS_MPU* bits, AND'ed with the currently-enabled PRM
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* MPU IRQs, and store the result into the two u32s pointed to by @events.
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* No return value.
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*/
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void omap44xx_prm_read_pending_irqs(unsigned long *events)
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{
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events[0] = _read_pending_irq_reg(OMAP4_PRM_IRQENABLE_MPU_OFFSET,
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OMAP4_PRM_IRQSTATUS_MPU_OFFSET);
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events[1] = _read_pending_irq_reg(OMAP4_PRM_IRQENABLE_MPU_2_OFFSET,
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OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET);
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}
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/**
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* omap44xx_prm_ocp_barrier - force buffered MPU writes to the PRM to complete
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*
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* Force any buffered writes to the PRM IP block to complete. Needed
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* by the PRM IRQ handler, which reads and writes directly to the IP
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* block, to avoid race conditions after acknowledging or clearing IRQ
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* bits. No return value.
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*/
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void omap44xx_prm_ocp_barrier(void)
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{
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omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST,
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OMAP4_REVISION_PRM_OFFSET);
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}
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/**
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* omap44xx_prm_save_and_clear_irqen - save/clear PRM_IRQENABLE_MPU* regs
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* @saved_mask: ptr to a u32 array to save IRQENABLE bits
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*
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* Save the PRM_IRQENABLE_MPU and PRM_IRQENABLE_MPU_2 registers to
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* @saved_mask. @saved_mask must be allocated by the caller.
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* Intended to be used in the PRM interrupt handler suspend callback.
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* The OCP barrier is needed to ensure the write to disable PRM
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* interrupts reaches the PRM before returning; otherwise, spurious
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* interrupts might occur. No return value.
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*/
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void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask)
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{
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saved_mask[0] =
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omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST,
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OMAP4_PRM_IRQSTATUS_MPU_OFFSET);
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saved_mask[1] =
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omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST,
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OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET);
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omap4_prm_write_inst_reg(0, OMAP4430_PRM_DEVICE_INST,
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OMAP4_PRM_IRQENABLE_MPU_OFFSET);
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omap4_prm_write_inst_reg(0, OMAP4430_PRM_DEVICE_INST,
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OMAP4_PRM_IRQENABLE_MPU_2_OFFSET);
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/* OCP barrier */
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omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST,
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OMAP4_REVISION_PRM_OFFSET);
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}
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/**
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* omap44xx_prm_restore_irqen - set PRM_IRQENABLE_MPU* registers from args
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* @saved_mask: ptr to a u32 array of IRQENABLE bits saved previously
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*
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* Restore the PRM_IRQENABLE_MPU and PRM_IRQENABLE_MPU_2 registers from
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* @saved_mask. Intended to be used in the PRM interrupt handler resume
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* callback to restore values saved by omap44xx_prm_save_and_clear_irqen().
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* No OCP barrier should be needed here; any pending PRM interrupts will fire
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* once the writes reach the PRM. No return value.
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*/
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void omap44xx_prm_restore_irqen(u32 *saved_mask)
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{
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omap4_prm_write_inst_reg(saved_mask[0], OMAP4430_PRM_DEVICE_INST,
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OMAP4_PRM_IRQENABLE_MPU_OFFSET);
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omap4_prm_write_inst_reg(saved_mask[1], OMAP4430_PRM_DEVICE_INST,
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OMAP4_PRM_IRQENABLE_MPU_2_OFFSET);
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}
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static int __init omap4xxx_prcm_init(void)
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{
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if (cpu_is_omap44xx())
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return omap_prcm_register_chain_handler(&omap4_prcm_irq_setup);
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return 0;
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}
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subsys_initcall(omap4xxx_prcm_init);
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