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30c8eb52cc
Currently driver wouldn't work properly if user asked for simplex transfer. The patch separates DMA rx and tx callbacks and finishes transfer correctly in any case. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
241 lines
5.9 KiB
C
241 lines
5.9 KiB
C
#ifndef DW_SPI_HEADER_H
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#define DW_SPI_HEADER_H
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#include <linux/io.h>
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#include <linux/scatterlist.h>
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#include <linux/gpio.h>
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/* Register offsets */
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#define DW_SPI_CTRL0 0x00
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#define DW_SPI_CTRL1 0x04
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#define DW_SPI_SSIENR 0x08
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#define DW_SPI_MWCR 0x0c
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#define DW_SPI_SER 0x10
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#define DW_SPI_BAUDR 0x14
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#define DW_SPI_TXFLTR 0x18
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#define DW_SPI_RXFLTR 0x1c
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#define DW_SPI_TXFLR 0x20
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#define DW_SPI_RXFLR 0x24
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#define DW_SPI_SR 0x28
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#define DW_SPI_IMR 0x2c
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#define DW_SPI_ISR 0x30
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#define DW_SPI_RISR 0x34
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#define DW_SPI_TXOICR 0x38
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#define DW_SPI_RXOICR 0x3c
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#define DW_SPI_RXUICR 0x40
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#define DW_SPI_MSTICR 0x44
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#define DW_SPI_ICR 0x48
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#define DW_SPI_DMACR 0x4c
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#define DW_SPI_DMATDLR 0x50
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#define DW_SPI_DMARDLR 0x54
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#define DW_SPI_IDR 0x58
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#define DW_SPI_VERSION 0x5c
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#define DW_SPI_DR 0x60
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/* Bit fields in CTRLR0 */
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#define SPI_DFS_OFFSET 0
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#define SPI_FRF_OFFSET 4
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#define SPI_FRF_SPI 0x0
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#define SPI_FRF_SSP 0x1
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#define SPI_FRF_MICROWIRE 0x2
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#define SPI_FRF_RESV 0x3
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#define SPI_MODE_OFFSET 6
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#define SPI_SCPH_OFFSET 6
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#define SPI_SCOL_OFFSET 7
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#define SPI_TMOD_OFFSET 8
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#define SPI_TMOD_MASK (0x3 << SPI_TMOD_OFFSET)
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#define SPI_TMOD_TR 0x0 /* xmit & recv */
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#define SPI_TMOD_TO 0x1 /* xmit only */
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#define SPI_TMOD_RO 0x2 /* recv only */
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#define SPI_TMOD_EPROMREAD 0x3 /* eeprom read mode */
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#define SPI_SLVOE_OFFSET 10
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#define SPI_SRL_OFFSET 11
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#define SPI_CFS_OFFSET 12
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/* Bit fields in SR, 7 bits */
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#define SR_MASK 0x7f /* cover 7 bits */
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#define SR_BUSY (1 << 0)
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#define SR_TF_NOT_FULL (1 << 1)
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#define SR_TF_EMPT (1 << 2)
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#define SR_RF_NOT_EMPT (1 << 3)
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#define SR_RF_FULL (1 << 4)
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#define SR_TX_ERR (1 << 5)
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#define SR_DCOL (1 << 6)
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/* Bit fields in ISR, IMR, RISR, 7 bits */
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#define SPI_INT_TXEI (1 << 0)
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#define SPI_INT_TXOI (1 << 1)
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#define SPI_INT_RXUI (1 << 2)
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#define SPI_INT_RXOI (1 << 3)
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#define SPI_INT_RXFI (1 << 4)
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#define SPI_INT_MSTI (1 << 5)
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/* Bit fields in DMACR */
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#define SPI_DMA_RDMAE (1 << 0)
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#define SPI_DMA_TDMAE (1 << 1)
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/* TX RX interrupt level threshold, max can be 256 */
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#define SPI_INT_THRESHOLD 32
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enum dw_ssi_type {
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SSI_MOTO_SPI = 0,
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SSI_TI_SSP,
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SSI_NS_MICROWIRE,
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};
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struct dw_spi;
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struct dw_spi_dma_ops {
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int (*dma_init)(struct dw_spi *dws);
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void (*dma_exit)(struct dw_spi *dws);
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int (*dma_transfer)(struct dw_spi *dws, int cs_change);
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};
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struct dw_spi {
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struct spi_master *master;
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struct spi_device *cur_dev;
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enum dw_ssi_type type;
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char name[16];
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void __iomem *regs;
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unsigned long paddr;
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int irq;
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u32 fifo_len; /* depth of the FIFO buffer */
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u32 max_freq; /* max bus freq supported */
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u16 bus_num;
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u16 num_cs; /* supported slave numbers */
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/* Message Transfer pump */
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struct tasklet_struct pump_transfers;
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/* Current message transfer state info */
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struct spi_message *cur_msg;
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struct spi_transfer *cur_transfer;
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struct chip_data *cur_chip;
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struct chip_data *prev_chip;
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size_t len;
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void *tx;
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void *tx_end;
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void *rx;
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void *rx_end;
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int dma_mapped;
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dma_addr_t rx_dma;
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dma_addr_t tx_dma;
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size_t rx_map_len;
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size_t tx_map_len;
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u8 n_bytes; /* current is a 1/2 bytes op */
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u8 max_bits_per_word; /* maxim is 16b */
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u32 dma_width;
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irqreturn_t (*transfer_handler)(struct dw_spi *dws);
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void (*cs_control)(u32 command);
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/* Dma info */
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int dma_inited;
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struct dma_chan *txchan;
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struct scatterlist tx_sgl;
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struct dma_chan *rxchan;
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struct scatterlist rx_sgl;
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unsigned long dma_chan_busy;
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struct device *dma_dev;
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dma_addr_t dma_addr; /* phy address of the Data register */
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struct dw_spi_dma_ops *dma_ops;
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void *dma_priv; /* platform relate info */
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/* Bus interface info */
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void *priv;
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#ifdef CONFIG_DEBUG_FS
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struct dentry *debugfs;
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#endif
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};
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static inline u32 dw_readl(struct dw_spi *dws, u32 offset)
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{
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return __raw_readl(dws->regs + offset);
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}
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static inline void dw_writel(struct dw_spi *dws, u32 offset, u32 val)
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{
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__raw_writel(val, dws->regs + offset);
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}
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static inline u16 dw_readw(struct dw_spi *dws, u32 offset)
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{
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return __raw_readw(dws->regs + offset);
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}
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static inline void dw_writew(struct dw_spi *dws, u32 offset, u16 val)
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{
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__raw_writew(val, dws->regs + offset);
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}
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static inline void spi_enable_chip(struct dw_spi *dws, int enable)
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{
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dw_writel(dws, DW_SPI_SSIENR, (enable ? 1 : 0));
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}
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static inline void spi_set_clk(struct dw_spi *dws, u16 div)
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{
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dw_writel(dws, DW_SPI_BAUDR, div);
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}
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static inline void spi_chip_sel(struct dw_spi *dws, struct spi_device *spi,
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int active)
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{
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u16 cs = spi->chip_select;
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int gpio_val = active ? (spi->mode & SPI_CS_HIGH) :
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!(spi->mode & SPI_CS_HIGH);
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if (dws->cs_control)
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dws->cs_control(active);
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if (gpio_is_valid(spi->cs_gpio))
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gpio_set_value(spi->cs_gpio, gpio_val);
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if (active)
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dw_writel(dws, DW_SPI_SER, 1 << cs);
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}
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/* Disable IRQ bits */
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static inline void spi_mask_intr(struct dw_spi *dws, u32 mask)
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{
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u32 new_mask;
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new_mask = dw_readl(dws, DW_SPI_IMR) & ~mask;
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dw_writel(dws, DW_SPI_IMR, new_mask);
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}
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/* Enable IRQ bits */
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static inline void spi_umask_intr(struct dw_spi *dws, u32 mask)
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{
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u32 new_mask;
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new_mask = dw_readl(dws, DW_SPI_IMR) | mask;
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dw_writel(dws, DW_SPI_IMR, new_mask);
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}
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/*
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* Each SPI slave device to work with dw_api controller should
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* has such a structure claiming its working mode (PIO/DMA etc),
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* which can be save in the "controller_data" member of the
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* struct spi_device.
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*/
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struct dw_spi_chip {
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u8 poll_mode; /* 1 for controller polling mode */
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u8 type; /* SPI/SSP/MicroWire */
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u8 enable_dma;
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void (*cs_control)(u32 command);
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};
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extern int dw_spi_add_host(struct device *dev, struct dw_spi *dws);
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extern void dw_spi_remove_host(struct dw_spi *dws);
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extern int dw_spi_suspend_host(struct dw_spi *dws);
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extern int dw_spi_resume_host(struct dw_spi *dws);
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extern void dw_spi_xfer_done(struct dw_spi *dws);
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/* platform related setup */
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extern int dw_spi_mid_init(struct dw_spi *dws); /* Intel MID platforms */
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#endif /* DW_SPI_HEADER_H */
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