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348d1bf75c
NVIDIA's Tegra114 added two more configuration parameter in pinmux i.e. rcv-sel and drive type. rcv-sel: Select between High and Normal VIL/VIH receivers. RCVR_SEL=1: High VIL/VIH RCVR_SEL=0: Normal VIL/VIH drv_type: Ouptput drive type: 33-50 ohm driver: 0x1 66-100ohm driver: 0x0 Add support of these parameters to be configure from DTS file. Tegra20 and Tegra30 does not support this configuration and hence initialize their pinmux structure with reg = -1. Originally written by Pritesh Raithatha. Changes by ldewangan: - remove drvtype_width as it is always 2. - Better describe the change. Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com> Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
207 lines
7.1 KiB
C
207 lines
7.1 KiB
C
/*
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* Driver for the NVIDIA Tegra pinmux
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*
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* Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#ifndef __PINMUX_TEGRA_H__
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#define __PINMUX_TEGRA_H__
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enum tegra_pinconf_param {
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/* argument: tegra_pinconf_pull */
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TEGRA_PINCONF_PARAM_PULL,
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/* argument: tegra_pinconf_tristate */
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TEGRA_PINCONF_PARAM_TRISTATE,
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/* argument: Boolean */
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TEGRA_PINCONF_PARAM_ENABLE_INPUT,
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/* argument: Boolean */
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TEGRA_PINCONF_PARAM_OPEN_DRAIN,
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/* argument: Boolean */
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TEGRA_PINCONF_PARAM_LOCK,
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/* argument: Boolean */
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TEGRA_PINCONF_PARAM_IORESET,
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/* argument: Boolean */
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TEGRA_PINCONF_PARAM_RCV_SEL,
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/* argument: Boolean */
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TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE,
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/* argument: Boolean */
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TEGRA_PINCONF_PARAM_SCHMITT,
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/* argument: Boolean */
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TEGRA_PINCONF_PARAM_LOW_POWER_MODE,
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/* argument: Integer, range is HW-dependant */
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TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH,
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/* argument: Integer, range is HW-dependant */
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TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH,
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/* argument: Integer, range is HW-dependant */
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TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING,
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/* argument: Integer, range is HW-dependant */
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TEGRA_PINCONF_PARAM_SLEW_RATE_RISING,
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/* argument: Integer, range is HW-dependant */
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TEGRA_PINCONF_PARAM_DRIVE_TYPE,
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};
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enum tegra_pinconf_pull {
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TEGRA_PINCONFIG_PULL_NONE,
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TEGRA_PINCONFIG_PULL_DOWN,
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TEGRA_PINCONFIG_PULL_UP,
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};
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enum tegra_pinconf_tristate {
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TEGRA_PINCONFIG_DRIVEN,
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TEGRA_PINCONFIG_TRISTATE,
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};
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#define TEGRA_PINCONF_PACK(_param_, _arg_) ((_param_) << 16 | (_arg_))
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#define TEGRA_PINCONF_UNPACK_PARAM(_conf_) ((_conf_) >> 16)
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#define TEGRA_PINCONF_UNPACK_ARG(_conf_) ((_conf_) & 0xffff)
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/**
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* struct tegra_function - Tegra pinctrl mux function
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* @name: The name of the function, exported to pinctrl core.
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* @groups: An array of pin groups that may select this function.
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* @ngroups: The number of entries in @groups.
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*/
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struct tegra_function {
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const char *name;
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const char * const *groups;
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unsigned ngroups;
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};
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/**
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* struct tegra_pingroup - Tegra pin group
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* @mux_reg: Mux register offset. -1 if unsupported.
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* @mux_bank: Mux register bank. 0 if unsupported.
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* @mux_bit: Mux register bit. 0 if unsupported.
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* @pupd_reg: Pull-up/down register offset. -1 if unsupported.
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* @pupd_bank: Pull-up/down register bank. 0 if unsupported.
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* @pupd_bit: Pull-up/down register bit. 0 if unsupported.
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* @tri_reg: Tri-state register offset. -1 if unsupported.
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* @tri_bank: Tri-state register bank. 0 if unsupported.
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* @tri_bit: Tri-state register bit. 0 if unsupported.
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* @einput_reg: Enable-input register offset. -1 if unsupported.
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* @einput_bank: Enable-input register bank. 0 if unsupported.
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* @einput_bit: Enable-input register bit. 0 if unsupported.
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* @odrain_reg: Open-drain register offset. -1 if unsupported.
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* @odrain_bank: Open-drain register bank. 0 if unsupported.
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* @odrain_bit: Open-drain register bit. 0 if unsupported.
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* @lock_reg: Lock register offset. -1 if unsupported.
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* @lock_bank: Lock register bank. 0 if unsupported.
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* @lock_bit: Lock register bit. 0 if unsupported.
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* @ioreset_reg: IO reset register offset. -1 if unsupported.
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* @ioreset_bank: IO reset register bank. 0 if unsupported.
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* @ioreset_bit: IO reset register bit. 0 if unsupported.
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* @rcv_sel_reg: Receiver select offset. -1 if unsupported.
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* @rcv_sel_bank: Receiver select bank. 0 if unsupported.
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* @rcv_sel_bit: Receiver select bit. 0 if unsupported.
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* @drv_reg: Drive fields register offset. -1 if unsupported.
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* This register contains the hsm, schmitt, lpmd, drvdn,
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* drvup, slwr, and slwf parameters.
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* @drv_bank: Drive fields register bank. 0 if unsupported.
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* @hsm_bit: High Speed Mode register bit. 0 if unsupported.
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* @schmitt_bit: Scmitt register bit. 0 if unsupported.
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* @lpmd_bit: Low Power Mode register bit. 0 if unsupported.
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* @drvdn_bit: Drive Down register bit. 0 if unsupported.
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* @drvdn_width: Drive Down field width. 0 if unsupported.
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* @drvup_bit: Drive Up register bit. 0 if unsupported.
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* @drvup_width: Drive Up field width. 0 if unsupported.
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* @slwr_bit: Slew Rising register bit. 0 if unsupported.
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* @slwr_width: Slew Rising field width. 0 if unsupported.
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* @slwf_bit: Slew Falling register bit. 0 if unsupported.
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* @slwf_width: Slew Falling field width. 0 if unsupported.
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* @drvtype_reg: Drive type fields register offset. -1 if unsupported.
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* @drvtype_bank: Drive type fields register bank. 0 if unsupported.
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* @drvtype_bit: Drive type register bit. 0 if unsupported.
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*
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* A representation of a group of pins (possibly just one pin) in the Tegra
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* pin controller. Each group allows some parameter or parameters to be
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* configured. The most common is mux function selection. Many others exist
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* such as pull-up/down, tri-state, etc. Tegra's pin controller is complex;
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* certain groups may only support configuring certain parameters, hence
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* each parameter is optional, represented by a -1 "reg" value.
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*/
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struct tegra_pingroup {
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const char *name;
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const unsigned *pins;
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unsigned npins;
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unsigned funcs[4];
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unsigned func_safe;
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s16 mux_reg;
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s16 pupd_reg;
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s16 tri_reg;
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s16 einput_reg;
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s16 odrain_reg;
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s16 lock_reg;
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s16 ioreset_reg;
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s16 rcv_sel_reg;
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s16 drv_reg;
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s16 drvtype_reg;
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u32 mux_bank:2;
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u32 pupd_bank:2;
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u32 tri_bank:2;
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u32 einput_bank:2;
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u32 odrain_bank:2;
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u32 ioreset_bank:2;
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u32 rcv_sel_bank:2;
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u32 lock_bank:2;
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u32 drv_bank:2;
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u32 drvtype_bank:2;
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u32 mux_bit:5;
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u32 pupd_bit:5;
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u32 tri_bit:5;
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u32 einput_bit:5;
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u32 odrain_bit:5;
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u32 lock_bit:5;
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u32 ioreset_bit:5;
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u32 rcv_sel_bit:5;
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u32 hsm_bit:5;
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u32 schmitt_bit:5;
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u32 lpmd_bit:5;
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u32 drvdn_bit:5;
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u32 drvup_bit:5;
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u32 slwr_bit:5;
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u32 slwf_bit:5;
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u32 drvtype_bit:5;
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u32 drvdn_width:6;
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u32 drvup_width:6;
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u32 slwr_width:6;
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u32 slwf_width:6;
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};
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/**
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* struct tegra_pinctrl_soc_data - Tegra pin controller driver configuration
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* @ngpios: The number of GPIO pins the pin controller HW affects.
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* @pins: An array describing all pins the pin controller affects.
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* All pins which are also GPIOs must be listed first within the
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* array, and be numbered identically to the GPIO controller's
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* numbering.
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* @npins: The numbmer of entries in @pins.
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* @functions: An array describing all mux functions the SoC supports.
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* @nfunctions: The numbmer of entries in @functions.
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* @groups: An array describing all pin groups the pin SoC supports.
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* @ngroups: The numbmer of entries in @groups.
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*/
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struct tegra_pinctrl_soc_data {
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unsigned ngpios;
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const struct pinctrl_pin_desc *pins;
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unsigned npins;
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const struct tegra_function *functions;
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unsigned nfunctions;
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const struct tegra_pingroup *groups;
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unsigned ngroups;
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};
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int tegra_pinctrl_probe(struct platform_device *pdev,
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const struct tegra_pinctrl_soc_data *soc_data);
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int tegra_pinctrl_remove(struct platform_device *pdev);
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#endif
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