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https://github.com/edk2-porting/linux-next.git
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52393ccc0a
set_wmb should not be used in the kernel because it just confuses the
code more and has no benefit. Since it is not currently used in the
kernel this patch removes it so that new code does not include it.
All archs define set_wmb(var, value) to do { var = value; wmb(); }
while(0) except ia64 and sparc which use a mb() instead. But this is
still moot since it is not used anyway.
Hasn't been tested on any archs but x86 and x86_64 (and only compiled
tested)
Signed-off-by: Steven Rostedt <rostedt@goodmis.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
494 lines
12 KiB
C
494 lines
12 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1994, 95, 96, 97, 98, 99, 2003 by Ralf Baechle
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* Copyright (C) 1996 by Paul M. Antoine
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* Copyright (C) 1999 Silicon Graphics
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* Kevin D. Kissell, kevink@mips.org and Carsten Langgaard, carstenl@mips.com
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* Copyright (C) 2000 MIPS Technologies, Inc.
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*/
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#ifndef _ASM_SYSTEM_H
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#define _ASM_SYSTEM_H
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#include <linux/types.h>
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#include <linux/irqflags.h>
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#include <asm/addrspace.h>
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#include <asm/cpu-features.h>
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#include <asm/dsp.h>
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#include <asm/ptrace.h>
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#include <asm/war.h>
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/*
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* read_barrier_depends - Flush all pending reads that subsequents reads
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* depend on.
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*
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* No data-dependent reads from memory-like regions are ever reordered
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* over this barrier. All reads preceding this primitive are guaranteed
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* to access memory (but not necessarily other CPUs' caches) before any
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* reads following this primitive that depend on the data return by
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* any of the preceding reads. This primitive is much lighter weight than
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* rmb() on most CPUs, and is never heavier weight than is
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* rmb().
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*
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* These ordering constraints are respected by both the local CPU
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* and the compiler.
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*
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* Ordering is not guaranteed by anything other than these primitives,
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* not even by data dependencies. See the documentation for
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* memory_barrier() for examples and URLs to more information.
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*
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* For example, the following code would force ordering (the initial
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* value of "a" is zero, "b" is one, and "p" is "&a"):
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*
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* <programlisting>
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* CPU 0 CPU 1
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*
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* b = 2;
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* memory_barrier();
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* p = &b; q = p;
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* read_barrier_depends();
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* d = *q;
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* </programlisting>
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*
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* because the read of "*q" depends on the read of "p" and these
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* two reads are separated by a read_barrier_depends(). However,
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* the following code, with the same initial values for "a" and "b":
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*
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* <programlisting>
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* CPU 0 CPU 1
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*
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* a = 2;
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* memory_barrier();
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* b = 3; y = b;
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* read_barrier_depends();
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* x = a;
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* </programlisting>
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*
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* does not enforce ordering, since there is no data dependency between
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* the read of "a" and the read of "b". Therefore, on some CPUs, such
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* as Alpha, "y" could be set to 3 and "x" to 0. Use rmb()
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* in cases like this where there are no data dependencies.
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*/
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#define read_barrier_depends() do { } while(0)
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#ifdef CONFIG_CPU_HAS_SYNC
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#define __sync() \
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__asm__ __volatile__( \
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".set push\n\t" \
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".set noreorder\n\t" \
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".set mips2\n\t" \
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"sync\n\t" \
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".set pop" \
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: /* no output */ \
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: /* no input */ \
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: "memory")
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#else
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#define __sync() do { } while(0)
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#endif
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#define __fast_iob() \
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__asm__ __volatile__( \
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".set push\n\t" \
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".set noreorder\n\t" \
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"lw $0,%0\n\t" \
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"nop\n\t" \
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".set pop" \
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: /* no output */ \
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: "m" (*(int *)CKSEG1) \
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: "memory")
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#define fast_wmb() __sync()
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#define fast_rmb() __sync()
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#define fast_mb() __sync()
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#define fast_iob() \
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do { \
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__sync(); \
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__fast_iob(); \
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} while (0)
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#ifdef CONFIG_CPU_HAS_WB
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#include <asm/wbflush.h>
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#define wmb() fast_wmb()
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#define rmb() fast_rmb()
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#define mb() wbflush()
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#define iob() wbflush()
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#else /* !CONFIG_CPU_HAS_WB */
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#define wmb() fast_wmb()
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#define rmb() fast_rmb()
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#define mb() fast_mb()
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#define iob() fast_iob()
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#endif /* !CONFIG_CPU_HAS_WB */
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#ifdef CONFIG_SMP
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#define smp_mb() mb()
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#define smp_rmb() rmb()
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#define smp_wmb() wmb()
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#define smp_read_barrier_depends() read_barrier_depends()
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#else
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#define smp_mb() barrier()
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#define smp_rmb() barrier()
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#define smp_wmb() barrier()
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#define smp_read_barrier_depends() do { } while(0)
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#endif
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#define set_mb(var, value) \
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do { var = value; mb(); } while (0)
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/*
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* switch_to(n) should switch tasks to task nr n, first
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* checking that n isn't the current task, in which case it does nothing.
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*/
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extern asmlinkage void *resume(void *last, void *next, void *next_ti);
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struct task_struct;
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#ifdef CONFIG_MIPS_MT_FPAFF
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/*
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* Handle the scheduler resume end of FPU affinity management. We do this
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* inline to try to keep the overhead down. If we have been forced to run on
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* a "CPU" with an FPU because of a previous high level of FP computation,
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* but did not actually use the FPU during the most recent time-slice (CU1
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* isn't set), we undo the restriction on cpus_allowed.
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*
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* We're not calling set_cpus_allowed() here, because we have no need to
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* force prompt migration - we're already switching the current CPU to a
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* different thread.
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*/
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#define switch_to(prev,next,last) \
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do { \
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if (cpu_has_fpu && \
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(prev->thread.mflags & MF_FPUBOUND) && \
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(!(KSTK_STATUS(prev) & ST0_CU1))) { \
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prev->thread.mflags &= ~MF_FPUBOUND; \
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prev->cpus_allowed = prev->thread.user_cpus_allowed; \
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} \
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if (cpu_has_dsp) \
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__save_dsp(prev); \
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next->thread.emulated_fp = 0; \
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(last) = resume(prev, next, next->thread_info); \
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if (cpu_has_dsp) \
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__restore_dsp(current); \
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} while(0)
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#else
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#define switch_to(prev,next,last) \
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do { \
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if (cpu_has_dsp) \
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__save_dsp(prev); \
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(last) = resume(prev, next, task_thread_info(next)); \
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if (cpu_has_dsp) \
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__restore_dsp(current); \
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} while(0)
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#endif
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/*
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* On SMP systems, when the scheduler does migration-cost autodetection,
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* it needs a way to flush as much of the CPU's caches as possible.
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*
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* TODO: fill this in!
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*/
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static inline void sched_cacheflush(void)
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{
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}
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static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
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{
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__u32 retval;
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if (cpu_has_llsc && R10000_LLSC_WAR) {
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unsigned long dummy;
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__asm__ __volatile__(
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" .set mips3 \n"
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"1: ll %0, %3 # xchg_u32 \n"
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" .set mips0 \n"
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" move %2, %z4 \n"
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" .set mips3 \n"
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" sc %2, %1 \n"
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" beqzl %2, 1b \n"
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#ifdef CONFIG_SMP
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" sync \n"
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#endif
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" .set mips0 \n"
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: "=&r" (retval), "=m" (*m), "=&r" (dummy)
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: "R" (*m), "Jr" (val)
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: "memory");
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} else if (cpu_has_llsc) {
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unsigned long dummy;
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__asm__ __volatile__(
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" .set mips3 \n"
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"1: ll %0, %3 # xchg_u32 \n"
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" .set mips0 \n"
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" move %2, %z4 \n"
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" .set mips3 \n"
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" sc %2, %1 \n"
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" beqz %2, 1b \n"
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#ifdef CONFIG_SMP
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" sync \n"
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#endif
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" .set mips0 \n"
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: "=&r" (retval), "=m" (*m), "=&r" (dummy)
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: "R" (*m), "Jr" (val)
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: "memory");
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} else {
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unsigned long flags;
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local_irq_save(flags);
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retval = *m;
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*m = val;
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local_irq_restore(flags); /* implies memory barrier */
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}
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return retval;
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}
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#ifdef CONFIG_64BIT
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static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val)
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{
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__u64 retval;
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if (cpu_has_llsc && R10000_LLSC_WAR) {
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unsigned long dummy;
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__asm__ __volatile__(
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" .set mips3 \n"
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"1: lld %0, %3 # xchg_u64 \n"
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" move %2, %z4 \n"
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" scd %2, %1 \n"
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" beqzl %2, 1b \n"
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#ifdef CONFIG_SMP
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" sync \n"
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#endif
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" .set mips0 \n"
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: "=&r" (retval), "=m" (*m), "=&r" (dummy)
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: "R" (*m), "Jr" (val)
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: "memory");
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} else if (cpu_has_llsc) {
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unsigned long dummy;
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__asm__ __volatile__(
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" .set mips3 \n"
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"1: lld %0, %3 # xchg_u64 \n"
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" move %2, %z4 \n"
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" scd %2, %1 \n"
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" beqz %2, 1b \n"
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#ifdef CONFIG_SMP
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" sync \n"
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#endif
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" .set mips0 \n"
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: "=&r" (retval), "=m" (*m), "=&r" (dummy)
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: "R" (*m), "Jr" (val)
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: "memory");
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} else {
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unsigned long flags;
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local_irq_save(flags);
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retval = *m;
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*m = val;
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local_irq_restore(flags); /* implies memory barrier */
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}
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return retval;
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}
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#else
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extern __u64 __xchg_u64_unsupported_on_32bit_kernels(volatile __u64 * m, __u64 val);
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#define __xchg_u64 __xchg_u64_unsupported_on_32bit_kernels
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#endif
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/* This function doesn't exist, so you'll get a linker error
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if something tries to do an invalid xchg(). */
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extern void __xchg_called_with_bad_pointer(void);
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static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
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{
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switch (size) {
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case 4:
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return __xchg_u32(ptr, x);
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case 8:
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return __xchg_u64(ptr, x);
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}
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__xchg_called_with_bad_pointer();
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return x;
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}
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#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
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#define tas(ptr) (xchg((ptr),1))
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#define __HAVE_ARCH_CMPXCHG 1
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static inline unsigned long __cmpxchg_u32(volatile int * m, unsigned long old,
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unsigned long new)
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{
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__u32 retval;
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if (cpu_has_llsc && R10000_LLSC_WAR) {
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__asm__ __volatile__(
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" .set push \n"
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" .set noat \n"
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" .set mips3 \n"
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"1: ll %0, %2 # __cmpxchg_u32 \n"
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" bne %0, %z3, 2f \n"
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" .set mips0 \n"
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" move $1, %z4 \n"
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" .set mips3 \n"
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" sc $1, %1 \n"
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" beqzl $1, 1b \n"
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#ifdef CONFIG_SMP
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" sync \n"
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#endif
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"2: \n"
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" .set pop \n"
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: "=&r" (retval), "=R" (*m)
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: "R" (*m), "Jr" (old), "Jr" (new)
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: "memory");
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} else if (cpu_has_llsc) {
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__asm__ __volatile__(
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" .set push \n"
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" .set noat \n"
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" .set mips3 \n"
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"1: ll %0, %2 # __cmpxchg_u32 \n"
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" bne %0, %z3, 2f \n"
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" .set mips0 \n"
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" move $1, %z4 \n"
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" .set mips3 \n"
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" sc $1, %1 \n"
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" beqz $1, 1b \n"
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#ifdef CONFIG_SMP
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" sync \n"
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#endif
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"2: \n"
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" .set pop \n"
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: "=&r" (retval), "=R" (*m)
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: "R" (*m), "Jr" (old), "Jr" (new)
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: "memory");
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} else {
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unsigned long flags;
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local_irq_save(flags);
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retval = *m;
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if (retval == old)
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*m = new;
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local_irq_restore(flags); /* implies memory barrier */
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}
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return retval;
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}
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#ifdef CONFIG_64BIT
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static inline unsigned long __cmpxchg_u64(volatile int * m, unsigned long old,
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unsigned long new)
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{
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__u64 retval;
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if (cpu_has_llsc) {
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__asm__ __volatile__(
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" .set push \n"
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" .set noat \n"
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" .set mips3 \n"
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"1: lld %0, %2 # __cmpxchg_u64 \n"
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" bne %0, %z3, 2f \n"
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" move $1, %z4 \n"
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" scd $1, %1 \n"
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" beqzl $1, 1b \n"
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#ifdef CONFIG_SMP
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" sync \n"
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#endif
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"2: \n"
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" .set pop \n"
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: "=&r" (retval), "=R" (*m)
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: "R" (*m), "Jr" (old), "Jr" (new)
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: "memory");
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} else if (cpu_has_llsc) {
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__asm__ __volatile__(
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" .set push \n"
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" .set noat \n"
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" .set mips3 \n"
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"1: lld %0, %2 # __cmpxchg_u64 \n"
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" bne %0, %z3, 2f \n"
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" move $1, %z4 \n"
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" scd $1, %1 \n"
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" beqz $1, 1b \n"
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#ifdef CONFIG_SMP
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" sync \n"
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#endif
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"2: \n"
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" .set pop \n"
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: "=&r" (retval), "=R" (*m)
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: "R" (*m), "Jr" (old), "Jr" (new)
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: "memory");
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} else {
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unsigned long flags;
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local_irq_save(flags);
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retval = *m;
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if (retval == old)
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*m = new;
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local_irq_restore(flags); /* implies memory barrier */
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}
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return retval;
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}
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#else
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extern unsigned long __cmpxchg_u64_unsupported_on_32bit_kernels(
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volatile int * m, unsigned long old, unsigned long new);
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#define __cmpxchg_u64 __cmpxchg_u64_unsupported_on_32bit_kernels
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#endif
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/* This function doesn't exist, so you'll get a linker error
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if something tries to do an invalid cmpxchg(). */
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extern void __cmpxchg_called_with_bad_pointer(void);
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static inline unsigned long __cmpxchg(volatile void * ptr, unsigned long old,
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unsigned long new, int size)
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{
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switch (size) {
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case 4:
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return __cmpxchg_u32(ptr, old, new);
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case 8:
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return __cmpxchg_u64(ptr, old, new);
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}
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__cmpxchg_called_with_bad_pointer();
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return old;
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}
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#define cmpxchg(ptr,old,new) ((__typeof__(*(ptr)))__cmpxchg((ptr), (unsigned long)(old), (unsigned long)(new),sizeof(*(ptr))))
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extern void set_handler (unsigned long offset, void *addr, unsigned long len);
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extern void set_uncached_handler (unsigned long offset, void *addr, unsigned long len);
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extern void *set_vi_handler (int n, void *addr);
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extern void *set_except_vector(int n, void *addr);
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extern unsigned long ebase;
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extern void per_cpu_trap_init(void);
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extern NORET_TYPE void die(const char *, struct pt_regs *);
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static inline void die_if_kernel(const char *str, struct pt_regs *regs)
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{
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if (unlikely(!user_mode(regs)))
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die(str, regs);
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}
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extern int stop_a_enabled;
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/*
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* See include/asm-ia64/system.h; prevents deadlock on SMP
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* systems.
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*/
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#define __ARCH_WANT_UNLOCKED_CTXSW
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#define arch_align_stack(x) (x)
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#endif /* _ASM_SYSTEM_H */
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